參數(shù)資料
型號: IDT71128S20YI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: Precision Adjustable (Programmable) Shunt Reference 8-TSSOP -40 to 125
中文描述: 256K X 4 STANDARD SRAM, 20 ns, PDSO32
封裝: 0.400 INCH, PLASTIC, SOJ-32
文件頁數(shù): 1/8頁
文件大小: 81K
代理商: IDT71128S20YI
FEBRUARY 2001
DSC-3483/09
1
2000 Integrated Device Technology, Inc.
Features
N
256K x 4 advanced high-speed CMOS static RAM
N
JEDEC revolutionary pinout (center power/GND) for
reduced noise.
N
Equal access and cycle times
— Commercial and Industrial: 12/15/20ns
N
One Chip Select plus one Output Enable pin
N
Bidirectional inputs and outputs directly
TTL-compatible
N
Low power consumption via chip deselect
N
Available in a 32-pin 400 mil Plastic SOJ.
Functional Block Diagram
Description
The IDT71128 is a 1,048,576-bit high-speed static RAM
organized as 256K x 4. It is fabricated using IDT’s high-perfor-
mance, high-reliability CMOS technology. This state-of-the-art
technology, combined with innovative circuit design techniques,
provides a cost-effective solution for high-speed memory needs.
The JEDEC centerpower/GND pinout reduces noise generation
and improves systemperformance.
The IDT71128 has an output enable pin which operates as fast
as 6ns, with address access times as fast as 12ns available. All
bidirectional inputs and outputs of the IDT71128 are TTL-compat-
ible and operation is froma single 5V supply. Fully static asyn-
chronous circuitry is used; no clocks or refreshes are required for
operation.
The IDT71128 is packaged in a 32-pin 400 ml Plastic SOJ.
A
17
A
0
I/O CONTROL
I/O
0
- I/O
3
CONTROL
LOGIC
WE
OE
CS
3483 drw 01
4
4
ADDRESS
DECODER
1,048,576-BIT
MEMORY
ARRAY
.
CMOS Static RAM
1 Meg (256K x 4-Bit)
Revolutionary Pinout
IDT71128
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