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參數(shù)資料
| 型號(hào)： | IDT71024S70TY |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CMOS STATIC RAM 1 MEG (128K x 8-BIT) |
| 中文描述： | 的CMOS靜態(tài)RAM 1邁可（128K的× 8位） |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 58K |
| 代理商： | IDT71024S70TY |
6
IDT71024S70
CMOS STATIC RAM 1MEG (128K x 8-BIT)
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
CONTROLLED TIMING)
(1, 2, 5, 7)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CS1
AND CS2
CONTROLLED TIMING)
(1, 2, 5)
NOTES:
1.
WE
must be HIGH,
CS1
must be HIGH, or CS2 must be LOW during all address transitions.
2. A write occurs during the overlap of a LOW
CS1
, HIGH CS2, and a LOW
WE
.
3. t
WR
is measured from the earlier of either
CS1
or
WE
going HIGH or CS2 going LOW to the end of the write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
CS1
LOW transition or the CS2 HIGH transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high impedance
state.
CS1
and CS2
must both be active during the t
CW
write period.
6. Transition is measured
±
200mV from steady state.
7.
OE
is continuously HIGH. During a
WE
controlled write cycle with
OE
LOW, t
WP
must be greater than or equal to t
WHZ
+ t
DW
to allow the I/O drivers to
turn off and data to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the
minimum write pulse is the specified t
WP
.
ADDRESS
CS1
WE
CS2
DATA
OUT
DATA
IN
3568 drw 07
(6)
(7)
(6)
(6)
DATA
IN
VALID
HIGH IMPEDANCE
t
WC
t
AW
t
AS
t
WHZ
t
WP
t
CHZ
t
OW
t
DW
t
DH
t
CW
(3)
t
WR
(4)
(4)
CS1
ADDRESS
WE
CS2
DATA
IN
3568 drw 08
t
AW
t
WC
t
CW
t
AS
t
WR
t
DW
t
DH
(3)
DATA
IN
VALID
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT71028S15Y | 制造商:Integrated Device Technology Inc 功能描述: |
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| IDT71124S12Y8 | 功能描述:IC SRAM 1MBIT 12NS 32SOJ RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步，DDR II 存儲(chǔ)容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
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