- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377290 > IDT71016S15PHGI (INTEGRATED DEVICE TECHNOLOGY INC) CMOS Static RAM 1 Meg (64K x 16-Bit) PDF資料下載
參數(shù)資料
| 型號： | IDT71016S15PHGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS Static RAM 1 Meg (64K x 16-Bit) |
| 中文描述： | 64K X 16 STANDARD SRAM, 15 ns, PDSO44 |
| 封裝： | 0.400 INCH, ROHS COMPLIANT, TSOP2-44 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 482K |
| 代理商： | IDT71016S15PHGI |
6.42
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2
(1)
NOTES:
1. A write occurs during the overlap of a LOW
CS
, LOW
BHE
or
BLE
, and a LOW
WE
.
2.
OE
is continuously HIGH. If during a
WE
controlled write cycle
OE
is LOW, t
WP
must be greater than or equal to t
WHZ
+ t
DW
to allow the I/O drivers to turn off and
data to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the
mnimumwrite pulse is as short as the specified t
WP
.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the
CS
LOW or
BHE
and
BLE
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV fromsteady state.
Timing Waveform of Write Cycle No. 1 (
WE
Controlled Timing)
(1,2,4)
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of
CS
,
BHE
, or
BLE
transition LOW; otherwise t
AA
is the limting parameter.
3. Transition is measured ±200mV fromsteady state.
ADDRESS
DATA
OUT
3210 drw 07
(3)
(3)
(3)
DATA
VALID
t
AA
t
RC
t
OE
t
OLZ
t
CHZ
t
OHZ
OUT
(3)
t
ACS
(3)
t
BLZ
t
CLZ
(2)
t
BE
t
OH
t
BHZ
(3)
(2)
,
OE
CS
BHE
,
BLE
ADDRESS
CS
DATA
IN
3210 drw 08
(5)
(5)
(5)
DATA
IN
VALID
t
WC
t
AS
t
WHZ
(2)
t
CW
t
CHZ
t
OW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
PREVIOUS DATA VALID
DATA VALID
BHE
,
BLE
t
BW
t
WP
(5)
t
BHZ
(3)
,
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT71016S15PHI | CMOS Static RAM 1 Meg (64K x 16-Bit) |
| IDT71024S70 | MPC5553MZP132 EVALUATION |
| IDT71024S70TY | CMOS STATIC RAM 1 MEG (128K x 8-BIT) |
| IDT71024 | CMOS STATIC RAM 1 MEG (128K x 8-BIT) |
| IDT71024S12TY | Octal Buffers And Line/MOS Drivers With 3-State Outputs 20-PDIP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT71016S15PHGI8 | 功能描述:IC SRAM 1MBIT 15NS 44TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,500 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-MSOP 包裝:帶卷 (TR) |
| IDT71016S15PHI | 功能描述:IC SRAM 1MBIT 15NS 44TSOP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標準包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
| IDT71016S15PHI8 | 功能描述:IC SRAM 1MBIT 15NS 44TSOP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標準包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
| IDT71016S15Y | 功能描述:IC SRAM 1MBIT 15NS 44SOJ RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標準包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
| IDT71016S15Y8 | 功能描述:IC SRAM 1MBIT 15NS 44SOJ RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標準包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。