參數(shù)資料
型號: IDT70V7319S133BF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: Photoelectric Sensor; Sensor Input Type:Optical; Sensing Range Max:50mm; Circuitry:SPDT; Leaded Process Compatible:No; Output Type:PNP; Peak Reflow Compatible (260 C):No; Sensing Mode:Fixed-Field
中文描述: 256K X 18 DUAL-PORT SRAM, 15 ns, PBGA208
封裝: FBGA-208
文件頁數(shù): 15/22頁
文件大?。?/td> 621K
代理商: IDT70V7319S133BF
6.42
IDT70V7319S
High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read
(
OE
= V
IL
)
(2)
R/
W
ADDRESS
An
An +1
An + 2
An + 2
An + 3
An + 4
DATA
IN
Dn + 2
CE
0
CLK
5629 drw 12
Qn
Qn + 3
DATA
OUT
CE
1
UB
/
LB
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
t
CH2
t
CL2
t
CYC2
READ
NOP
READ
t
SD
t
HD
(3)
(1)
t
SW
t
HW
WRITE
(4)
NOTES:
1. Output state (High, Low, or High-impedance) is determned by the previous cycle control signals.
2.
CE
0
,
UB
/
LB
, and
ADS
= V
IL
; CE
1
,
CNTEN
, and
REPEAT
= V
IH
. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since
ADS
= V
IL
constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
R/
W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
An + 5
DATA
IN
Dn + 3
Dn + 2
CE
0
CLK
5629 drw 13
DATA
OUT
Qn
Qn + 4
CE
1
UB
/
LB
OE
t
CH2
t
CL2
t
CYC2
t
CKLZ
t
CD2
t
OHZ
t
CD2
t
SD
t
HD
READ
WRITE
READ
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
(3)
(1)
t
SW
t
HW
(4)
Timing Waveform of Pipelined Read-to-Write-to-Read (
OE
Controlled)
(2)
NOTES:
1. Output state (High, Low, or High-impedance) is determned by the previous cycle control signals.
2.
CE
0
,
UB
/
LB
, and
ADS
= V
IL
; CE
1
,
CNTEN
, and
REPEAT
= V
IH
.
3. Addresses do not have to be accessed sequentially since
ADS
= V
IL
constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timng does not meet requirements for fastest speed grade. This waveformindicates how logically it could be done if timng so allows.
相關(guān)PDF資料
PDF描述
IDT70V7319S133BFI HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V7319S133DD HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V7319S133DDI HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V7319S200DDI HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V7319S166BC HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
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