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參數(shù)資料
| 型號： | IDT70V639S15PRFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM |
| 中文描述： | 128K X 18 DUAL-PORT SRAM, 15 ns, PQFP128 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128 |
| 文件頁數(shù)： | 2/23頁 |
| 文件大?。?/td> | 187K |
| 代理商： | IDT70V639S15PRFI |
IDT70V639S
High-Speed 3.3V 128K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Preliminary
2
The IDT70V639 is a high-speed 128K x 18 Asynchronous Dual-Port
Static RAM. The IDT70V639 is designed to be used as a stand-alone
2304K-bit Dual-Port RAMor as a combination MASTER/SLAVE Dual-
Port RAMfor 36-bit-or-more word system Using the IDT MASTER/
SLAVE Dual-Port RAMapproach in 36-bit or wider memory system
applications results in full-speed, error-free operation without the need for
additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permt independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (either
CE
0
or CE
1
) permt the
on-chip circuitry of each port to enter a very low standby power mode.
The 70V639 can support an operating voltage of either 3.3V or 2.5V
on one or both ports, controlled by the OPT pins. The power supply for
the core of the device (V
DD
) remains at 3.3V.
!"
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V) and 2.5V if OPT pin for that port is
set to V
IL
(0V).
3. All V
SS
pins must be connected to ground.
4. Package body is approximately 15mmx 15mmx 1.4mmwith 0.8mmball pitch.
5. This package code is used to reference the package diagram
6. This text does not indicate orientation of the actual part-marking.
17
16
15
14
12
13
10
9
8
7
6
5
4
3
2
1
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
I/O
9L
NC
V
SS
A
4L
INT
L
SEM
L
NC
A
8L
A
12L
A
16L
V
SS
NC
OPT
L
A
0L
NC
V
SS
NC
NC
A
1L
A
5L
BUSY
L
V
SS
CE
0L
CE
1L
NC
A
9L
A
13L
NC
I/O
8L
V
DDQR
V
SS
V
DDQL
I/O
9R
V
DDQR
V
DD
A
2L
A
6
L
R/
W
L
V
SS
UB
L
A
10L
A
14L
NC
NC
I/O
8R
V
DD
I/O
11L
V
SS
I/O
10L
NC
V
DD
A
3L
NC
OE
L
NC
I/O
11R
V
DDQR
I/O
10R
V
DDQL
NC
NC
V
SS
NC
V
SS
I/O
12L
NC
V
DD
NC
V
DDQR
I/O
12R
V
DDQL
V
DD
V
SS
V
SS
NC
I/O
14L
V
DDQR
V
DDQL
NC
I/O
15R
V
SS
I/O
7R
V
DDQL
I/O
7L
A
15L
A
11L
A
7L
LB
L
I/O
6L
NC
V
SS
NC
V
SS
I/O
6R
NC
NC
V
DDQL
I/O
5L
NC
V
DD
NC
V
SS
I/O
5R
V
SS
V
DDQR
I/O
3R
V
DDQL
I/O
4R
V
SS
I/O
4L
V
SS
I/O
3L
NC
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
I/O
1R
NC
V
SS
NC
I/O
15L
A
16R
A
12R
A
8R
NC
V
DD
SEM
R
INT
R
V
DDQR
NC
I/O
1L
NC
V
SS
NC
I/O
17R
NC
A
13R
A
9R
NC
CE
0R
CE
1R
V
DD
V
SS
BUSY
R
V
SS
V
DD
V
SS
V
DDQL
I/O
0R
V
DDQR
NC
I/O
17L
V
DDQL
NC
NC
A
14R
A
10R
UB
R
V
SS
NC
NC
V
SS
I/O
2R
NC
V
SS
NC
V
DD
A
15R
A
11R
A
7R
LB
R
OE
R
M/
S
R/
W
R
V
DDQL
I/O
2L
OPT
R
NC
I/O
0L
70V639BF
BF-208
(5)
208-Ball BGA
Top View
(6)
5621 tbl 02b
I/O
13L
I/O
14R
V
SS
I/O
13R
V
SS
I/O
16R
I/O
16L
V
DDQR
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
SS
NC
NC
V
DDQR
V
SS
V
DD
V
SS
NC
V
DD
V
DD
TDO
TDI
TCK
TMS
TRST
V
SS
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