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參數(shù)資料
| 型號： | IDT70V639S10BCI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM |
| 中文描述： | 高速3.3 128K的× 18 ASYNCHRONO美國雙端口靜態(tài)RAM |
| 文件頁數(shù)： | 18/23頁 |
| 文件大?。?/td> | 187K |
| 代理商： | IDT70V639S10BCI |
IDT70V639S
High-Speed 3.3V 128K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Preliminary
18
The IDT70V639 provides two ports with separate control, address
and I/O pins that permt independent access for reads or writes to any
location in memory. The IDT70V639 has an automatic power down feature
controlled by
CE
. The
CE
0
and CE
1
control the on-chip power down
circuitry that permts the respective port to go into a standby mode when
not selected (
CE
= HIGH). When a port is enabled, access to the entire
memory array is permtted.
)
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (
INT
L
) is asserted when the right port writes to memory location
3FFFE (HEX), where a write is defined as
CE
R
= R/
W
R
= V
IL
per the
Truth Table. The left port clears the interrupt through access of
address location 3FFFE when
CE
L
=
OE
L
= V
IL
, R/
W
is a "don't care".
Likewise, the right port interrupt flag (
INT
R
) is asserted when the left
port writes to memory location 3FFFF (HEX) and to clear the interrupt
flag (
INT
R
), the right port must read the memory location 3FFFF. The
message (18 bits) at 3FFFE or 3FFFF is user-defined since it is an
addressable SRAMlocation. If the interrupt function is not used,
address locations 3FFFE and 3FFFF are not used as mail boxes, but
as part of the randomaccess memory. Refer to Truth Table III for
the interrupt operation.
&'&()3*
7,,
BUSY
7(
NOTES:
1. Pins
BUSY
L
and
BUSY
R
are both outputs when the part is configured as a master. Both are inputs when configured as a slave.
BUSY
outputs on the IDT70V639
are push-pull, not open drain outputs. On slaves the
BUSY
input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t
APS
is not met, either
BUSY
L
or
BUSY
R
= LOW will result.
BUSY
L
and
BUSY
R
outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when
BUSY
L
outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when
BUSY
R
outputs are driving LOW regardless of actual logic level on the pin.
&'&(3*90'0E
"
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V639.
2. There are eight semaphore flags written to via I/O
0
and read fromall I/O's (I/O
0
-I/O
17
). These eight semaphores are addressed by A
0
- A
2
.
3.
CE
= V
IH
,
SEM
= V
IL
to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Inputs
Outputs
Function
CE
L
CE
R
A
OL
-A
16L
A
OR
-A
16R
BUSY
L
(1)
BUSY
R
(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit
(3)
5621 tbl 17
Functions
D
0
- D
17
Left
D
0
- D
17
Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
5621 tbl 18
相關PDF資料 |
PDF描述 |
|---|---|
| IDT70V639S10BF | HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM |
| IDT70V639S10BFI | HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM |
| IDT70V639S10PRF | HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM |
| IDT70V639S10PRFI | HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM |
| IDT70V639S12BC | HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT70V639S10BF | 功能描述:IC SRAM 2.25MBIT 10NS 208FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOIC 包裝:帶卷 (TR) |
| IDT70V639S10BF8 | 功能描述:IC SRAM 2.25MBIT 10NS 208FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOIC 包裝:帶卷 (TR) |
| IDT70V639S10PRF | 功能描述:IC SRAM 2.25MBIT 10NS 128TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOIC 包裝:帶卷 (TR) |
| IDT70V639S10PRF8 | 功能描述:IC SRAM 2.25MBIT 10NS 128TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOIC 包裝:帶卷 (TR) |
| IDT70V639S10PRFG | 功能描述:IC SRAM 2.25MBIT 10NS 128TQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOIC 包裝:帶卷 (TR) |
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