參數(shù)資料
型號: IDT70V25S55G
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM
中文描述: 8K X 16 DUAL-PORT SRAM, 55 ns, CPGA84
封裝: 1.120 X 1.120 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-84
文件頁數(shù): 10/17頁
文件大小: 276K
代理商: IDT70V25S55G
6.39
10
IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
BUSY TIMING (M/
S
= V
IL
)
t
WB
t
WH
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
Write Data Valid to Read Data Delay
(1)
BUSY
Input to Write
(4)
Write Hold After
BUSY
(5)
0
20
0
25
0
ns
ns
25
55
60
80
ns
t
DDD
50
55
75
ns
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(6)
IDT70V25X25
Min.
IDT70V25X35
Min.
IDT70V25X55
Min.
Symbol
BUSY TIMING (M/
S
= V
IH
)
t
BAA
t
BDA
t
BAC
t
BDC
Parameter
Max.
Max.
Max.
Unit
BUSY
Access Time from Address Match
BUSY
Disable Time from Address Not Matched
BUSY
Access Time from Chip Low
BUSY
Disable Time from Chip High
Arbitration Priority Set-up Time
(2)
BUSY
Disable to Valid Data
(3)
Write Hold After
BUSY
(5)
25
25
25
25
35
35
35
35
45
45
45
45
ns
ns
ns
ns
t
APS
5
5
5
ns
t
BDD
t
WH
20
35
25
35
25
45
ns
ns
TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND
BUSY
(M/
S
= V
IH
)
(2,4,5)
2944 drw 12
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/
W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD(3)
t
WDD
t
BAA
2944 tbl 14
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND
BUSY
(M/
S
= V
IH
)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
– t
WP
(actual), or t
DDD
– t
DW
(actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. "X" is part numbers indicates power rating (S or L).
NOTES:
1. To ensure that the earlier of the two ports wins. t
APS
is ignored for M/
S
= V
IL
(slave).
2.
CE
L
=
CE
R
= V
IL
.
3.
OE
= V
IL
for the reading port.
4. If M/
S
= V
IL
(slave),
BUSY
is an input. Then for this example
BUSY
"A"
= V
IH
and
BUSY
"B"
input is shown above.
5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A".
相關PDF資料
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IDT70V25S55J HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM
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