參數(shù)資料
型號: IDT70V15L15PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 3.3V 16/8K X 9 DUAL-PORT STATIC RAM
中文描述: 8K X 9 DUAL-PORT SRAM, 15 ns, PQFP80
封裝: 14 X 14 MM, 1.40 MM HEIGHT, TQFP-80
文件頁數(shù): 14/18頁
文件大?。?/td> 167K
代理商: IDT70V15L15PF
6.42
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
P
R
E
L
I
M
I
N
A
R
Y
P
R
E
PRELIMINARY
&'(((B(
#
NOTES:
1. Assumes
BUSY
L
=
BUSY
R
= V
IH
.
2. If
BUSY
L
= V
IL
, then no change.
3. If
BUSY
R
= V
IL
, then no change.
4. A
13
is a NC for IDT70V15, therefore Interrupt Addresses are 1FFF and 1FFE.
Left Port
Right Port
Function
R/
W
L
CE
L
OE
L
A
13L
-A
0L
INT
L
R/
W
R
CE
R
OE
R
A
13R
-A
0R
INT
R
L
L
X
3FFF
(4)
X
X
X
X
X
L
(2)
Set Right
INT
R
Flag
X
X
X
X
X
X
L
L
3FFF
(4)
H
(3)
Reset Right
INT
R
Flag
X
X
X
X
L
(3)
L
L
X
3FFE
(4)
X
Set Left
INT
L
Flag
X
L
L
3FFE
(4)
H
(2)
X
X
X
X
X
Reset Left
INT
L
Flag
5669 tbl 15
&'(4B++
'
BUSY
NOTES:
1. Pins
BUSY
L
and
BUSY
R
are both outputs when the part is configured as a master. Both are inputs when configured as a slave.
BUSY
X
outputs on the
IDT70V16/5 are push-pull, not open drain outputs. On slaves the
BUSY
X
input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t
APS
is not met, either
BUSY
L
or
BUSY
R
= LOW will result.
BUSY
L
and
BUSY
R
outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when
BUSY
L
outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when
BUSY
R
outputs are driving LOW regardless of actual logic level on the pin.
4. A
13
a NC for IDT70V15, Address comparison will be for A
0
- A
12
.
&'4B08&C
!#
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V16/5.
2. There are eight semaphore flags written to via I/O
0
and read fromall I/O
s
(I/O
0
- I/O
8
). These eight semaphores are addressed by A
0
- A
2
.
e.
CE
= V
IH
,
SEM
= V
IL
to access the semaphores. Refer to the semaphore Read/Write Truth Table.
Inputs
Outputs
Function
CE
L
CE
R
A
OL
-A
13L
A
OR
-A
13R
BUSY
L
(1)
BUSY
R
(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit
(3)
5669 tbl 16
Functions
D
0
- D
8
Left
D
0
- D
8
Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
5669 tbl 17
相關(guān)PDF資料
PDF描述
IDT70V15L15PFI HIGH-SPEED 3.3V 16/8K X 9 DUAL-PORT STATIC RAM
IDT70V15L20J HIGH-SPEED 3.3V 16/8K X 9 DUAL-PORT STATIC RAM
IDT70V15L20JI HIGH-SPEED 3.3V 16/8K X 9 DUAL-PORT STATIC RAM
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