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參數(shù)資料
| 型號(hào)： | IDT70V09 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CABLE 26 COND 100FT TWISTED PAIR |
| 中文描述： | 高速3.3 128K的× 8雙端口靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 6/15頁(yè) |
| 文件大?。?/td> | 190K |
| 代理商： | IDT70V09 |
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6.42
IDT70V9379L
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
14
Depth and Width Expansion
The IDT70V9379 features dual chip enables (refer to Truth Table I)
inordertofacilitaterapidandsimpledepthexpansionwithnorequirements
for external logic. Figure 4 illustrates how to control the varioius chip
enables in order to expand two devices in depth.
TheIDT70V9379canalsobeusedinapplicationsrequiringexpanded
width, as indicated in Figure 4. Since the banks are allocated at the
discretionoftheuser,theexternalcontrollercanbesetuptodrivetheinput
signals for the various devices as required to allow for 36-bit or wider
applications.
4857 drw 18
IDT70V9379
CE0
CE1
CE0
CE1
A15
CE1
CE0
VCC
IDT70V9379
Control Inputs
CNTRST
CLK
ADS
CNTEN
R/
W
LB, UB
OE
Figure 4. Depth and Width Expansion with IDT70V9379
Functional Description
The IDT70V9379 provides a true synchronous Dual-Port Static RAM
interface. Registered inputs provide minimal set-up and hold times on
address,data,andallcriticalcontrolinputs.Allinternalregistersareclocked
ontherisingedgeoftheclocksignal,however,theself-timedinternalwrite
pulse is independent of the LOW to HIGH transition of the clock signal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to staff the
operationoftheaddresscountersforfastinterleavedmemoryapplications.
CE0 = VIL and CE1 = VIH for one clock cycle will power down the
internalcircuitrytoreducestaticpowerconsumption.Multiplechipenables
allow easier banking of multiple IDT70V9379's for depth expansion
configurations.WhenthePipelinedoutputmodeisenabled,twocyclesare
required with
CE0 = VIL and CE1 = VIH to re-activate the outputs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT70V09L | Twisted Pair Flat Cable, 1700/34 28 AWG, .050 (1.27) |
| IDT70V09L15PF | HIGH-SPEED 3.3V 128K x 8 DUAL-PORT STATIC RAM |
| IDT70V09L15PFI | CABLE 34 COND 100FT TWISTED PAIR |
| IDT72T40108 | Insulation Displacement (IDC) Connector; No. of Contacts:36; Contact Termination:IDC; Gender:Female; Pitch Spacing:0.1" RoHS Compliant: Yes |
| IDT72T40108L10BB | 2.5 VOLT HIGH-SPEED TeraSync?? DDR/SDR FIFO 40-BIT CONFIGURATION |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT70V09L15PF | 功能描述:IC SRAM 1MBIT 15NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) |
| IDT70V09L15PF8 | 功能描述:IC SRAM 1MBIT 15NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT70V09L15PFG | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 1MBIT 15NS 100TQFP |
| IDT70V09L15PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 1MBIT 15NS 100TQFP |
| IDT70V09L20PF | 功能描述:IC SRAM 1MBIT 20NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
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