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參數(shù)資料
| 型號： | IDT70V08S35PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 64K X 8 DUAL-PORT SRAM, 35 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 163K |
| 代理商： | IDT70V08S35PF |
17
IDT70V08S/L
High-Speed 64K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
The IDT70V08 provides two ports with separate control, address
and I/O pins that permt independent access for reads or writes to any
location in memory. The IDT70V08 has an automatic power down
feature controlled by
CE
. The
CE
0
and CE
1
control the on-chip power
down circuitry that permts the respective port to go into a standby
mode when not selected (
CE
HIGH). When a port is enabled, access
to the entire memory array is permtted.
4
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (
INT
L
) is asserted when the right port writes to memory location
FFFE (HEX), where a write is defined as
CE
R
= R/
W
R
= V
IL
per the
Truth Table. The left port clears the interrupt through access of
address location FFFE when
CE
L
=
OE
L
= V
IL
, R/
W
is a "don't care".
Likewise, the right port interrupt flag (
INT
R
) is asserted when the left
port writes to memory location FFFF (HEX) and to clear the interrupt
flag (INT
R
), the right port must read the memory location FFFF. The
message (8 bits) at FFFE or FFFF is user-defined since it is an
addressable SRAMlocation. If the interrupt function is not used,
)2)$,C
''
BUSY
$
Inputs
>#
NOTES:
1.
Pins
BUSY
L
and
BUSY
R
are both outputs when the part is configured as a master. Both are inputs when configured as a slave.
BUSY
outputs on the IDT70V08 are push-
pull, not open drain outputs. On slaves the
BUSY
input internally inhibits writes.
"L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and
enable inputs of this port. If t
APS
is not met, either
BUSY
L
or
BUSY
R
= LOW will result.
BUSY
L
and
BUSY
R
outputs can not be LOW simultaneously.
Writes to the left port are internally ignored when
BUSY
L
outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSY
R
outputs are driving LOW regardless of actual logic level on the pin.
Refer to Chip Enable Truth Table.
2.
3.
4.
)2)$,4C8&*2*D
!!"#
NOTES:
1.
2. There are eight semaphore flags written to via I/O
0
and read fromall I/O's (I/O
0
-I/O
7
). These eight semaphores are addressed by A
0
- A
2
.
3.
CE
= V
IH
,
SEM
= V
IL
to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
This table denotes a sequence of events for only one of the eight semaphores on the IDT70V08.
Outputs
Function
CE
L
CE
R
A
OL
-A
15L
A
OR
-A
15R
BUSY
L
(1)
BUSY
R
(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit
(3)
3740 tbl 17
Functions
D
0
- D
7
Left
D
0
- D
7
Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
3740 tbl 18
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| IDT70V08S35PF8 | 功能描述:IC SRAM 512KBIT 35NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，同步 存儲容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT70V09L15PF | 功能描述:IC SRAM 1MBIT 15NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) |
| IDT70V09L15PF8 | 功能描述:IC SRAM 1MBIT 15NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，同步 存儲容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT70V09L15PFG | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 1MBIT 15NS 100TQFP |
| IDT70V09L15PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 1MBIT 15NS 100TQFP |
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