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參數(shù)資料
| 型號： | IDT70V08S15PFI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 高速64K的× 8雙端口靜態(tài)RAM |
| 文件頁數(shù)： | 19/20頁 |
| 文件大小： | 163K |
| 代理商： | IDT70V08S15PFI |
19
IDT70V08S/L
High-Speed 64K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
D
3740 drw 18
0
D
Q
WRITE
D
0
WRITE
D
Q
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
L PORT
R PORT
SEMAPHORE
READ
SEMAPHORE
READ
,
is in use. The semaphores provide a hardware assist for a use assignment
method called
“
Token Passing Allocation.
”
In this method, the state of a
semaphore latch is used as a token indicating that a shared resource is
in use. If the left processor wants to use this resource, it requests the token
by setting the latch. This processor then verifies its success in setting the
latch by reading it. If it was successful, it proceeds to assume control over
the shared resource. If it was not successful in setting the latch, it determnes
that the right side processor has set the latch first, has the token and is using
the shared resource. The left processor can then either repeatedly request
that semaphore
’
s status or remove its request for that semaphore to
performanother task and occasionally attempt again to gain control of the
token via the set and test sequence. Once the right side has relinquished
the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
The eight semaphore flags reside within the IDT70V08 in a
separate memory space fromthe Dual-Port RAM. This address space
is accessed by placing a low input on the
SEM
pin (which acts as a chip
select for the semaphore flags) and using the other control pins
(Address,
CE
, and R/
W
) as they would be used in accessing a
standard Static RAM. Each of the flags has a unique address which
can be accessed by either side through address pins A
0
–
A
2
. When
accessing the semaphores, none of the other address pins has any
effect.
When writing to a semaphore, only data pin D
0
is used. If a low level
is written into an unused semaphore location, that flag will be set to a
zero on that side and a one on the other side (see Truth Table VI). That
semaphore can now only be modified by the side showing the zero.
When a one is written into the same location fromthe same side, the
flag will be set to a one for both sides (unless a semaphore request
fromthe other side is pending) and then can be written to by both sides.
The fact that the side which is able to write a zero into a semaphore
subsequently locks out writes fromthe other side is what makes
semaphore flags useful in interprocessor communications. (A thor-
ough discussion on the use of this feature follows shortly.) A zero
written into the same location fromthe other side will be stored in the
semaphore request latch for that side until the semaphore is freed by
the first side.
When a semaphore flag is read, its value is spread into all data bits
so that a flag that is a one reads as a one in all data bits and a flag
containing a zero reads as all zeros. The read value is latched into one
side
’
s output register when that side's semaphore select (
SEM
) and
output enable (
OE
) signals go active. This serves to disallow the
semaphore fromchanging state in the mddle of a read cycle due to a
write cycle fromthe other side. Because of this latch, a repeated read
of a semaphore in a test loop must cause either signal (
SEM
or
OE
) to
go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no systemlevel contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Table VI). As an example, assume a processor
writes a zero to the left port at a free semaphore location. On a subsequent
read, the processor will verify that it has written successfully to that location
and will assume control over the resource in question. Meanwhile, if a
processor on the right side attempts to write a zero to the same semaphore
flag it will fail, as will be verified by the fact that a one will be read fromthat
semaphore on the right side during subsequent read. Had a sequence
of READ/WRITE been used instead, systemcontention problems could
have occurred during the gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side
’
s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first side
’
s request
latch. The second side
’
s flag will now stay LOW until its semaphore request
latch is written to a one. Fromthis it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire systemcan hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timng is when both sides request
a single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
both requests arrive at the same time, the assignment will be arbitrarily
made to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
secure. As with any powerful programmng technique, if semaphores
are msused or msinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
handled via the initialization programat power-up. Since any sema-
phore request flag which contains a zero must be reset to a one, all
semaphores on both sides should have a one written into themat
initialization fromboth sides to assure that they will be free when
needed.
Figure 4. IDT70V08 Semaphore Logic
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| IDT70V08S20PF | 功能描述:IC SRAM 512KBIT 20NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，同步 存儲容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
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| IDT70V08S25PF | 功能描述:IC SRAM 512KBIT 25NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，同步 存儲容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
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