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參數(shù)資料
| 型號： | IDT70V08L |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 高速64K的× 8雙端口靜態(tài)RAM |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 163K |
| 代理商： | IDT70V08L |
IDT70V08S/L
High-Speed 64K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
12
NOTES:
1. Port-to-port delay through RAMcells fromwriting port to reading port, refer to "Timng Waveformof Write with Port-to-Port Read and BUSY (M/S = V
IH
)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
–
t
WP
(actual), or t
DDD
–
t
DW
(actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
7. Industrial temperature: for specific speeds, packages and powers contact yuor sales office.
82(:2
()'*+,
;!<#
70V08X15
Com'l Only
70V08X20
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY
TIMING (M/
S
=V
IH
)
t
BAA
BUSY
Access Time fromAddress Match
____
15
____
20
ns
t
BDA
BUSY
Disable Time fromAddress Not Matched
____
15
____
20
ns
t
BAC
BUSY
Access Time fromChip Enable Low
____
15
____
20
ns
t
BDC
BUSY
Access Time fromChip Enable High
____
15
____
20
ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(3)
____
17
____
35
ns
t
WH
Write Hold After
BUSY
(5)
12
____
15
____
ns
BUSY
TIMING (M/
S
=V
IL
)
t
WB
BUSY
Input to Write
(4)
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
12
____
15
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
30
____
45
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
25
____
30
ns
3740 tbl 14a
70V08X25
Com'l Only
70V08X35
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY
TIMING (M/
S
=V
IH
)
t
BAA
BUSY
Access Time fromAddress Match
____
25
____
35
ns
t
BDA
BUSY
Disable Time fromAddress Not Matched
____
25
____
35
ns
t
BAC
BUSY
Access Time fromChip Enable Low
____
25
____
35
ns
t
BDC
BUSY
Access Time fromChip Enable High
____
25
____
35
ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(3)
____
35
____
40
ns
t
WH
Write Hold After
BUSY
(5)
20
____
25
____
ns
BUSY
TIMING (M/
S
=V
IL
)
t
WB
BUSY
Input to Write
(4)
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
20
____
25
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
55
____
65
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
50
____
60
ns
3740 tbl 14b
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