參數資料
型號: IDT70V07S25PFI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
中文描述: 32K X 8 DUAL-PORT SRAM, 25 ns, PQFP80
封裝: 14 X 14 MM, 1.40 MM HEIGHT, TQFP-80
文件頁數: 11/18頁
文件大?。?/td> 174K
代理商: IDT70V07S25PFI
11
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(6)
2943 drw 13
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/
W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
t
BAA
Timing Waveform of Write with Port-to-Port Read and
BUSY
(2,4,5)
NOTES:
1. To ensure that the earlier of the two ports wins. t
APS
is ignored for M/
S
= V
IL
(SLAVE).
2.
CE
L
=
CE
R
= V
IL
3.
OE
= V
IL
for the reading port.
4. If M/
S
= V
IL
(SLAVE), then
BUSY
is an input (
BUSY
"A"
= V
IH
and
BUSY
"B"
= "don't care", for this example).
5. All timng is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite fromport "A".
NOTES:
1. Port-to-port delay through RAMcells fromwriting port to reading port, refer to "Timng Waveformof Write with Port-to-Port Read and
BUSY
".
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
– t
WP
(actual) or t
DDD
– t
DW
(actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
70V07X25
Com'l
& Ind
70V07X35
Com'l Only
70V07X55
Com'l Only
Symbol
Parameter
Mn.
Max.
Mn.
Max.
Mn.
Max.
Unit
BUSY
TIMING (M/
S
= V
IH
)
t
BAA
BUSY
Access Time fromAddress
____
25
____
35
____
45
ns
t
BDA
BUSY
Disable Time fromAddress
____
25
____
35
____
45
ns
t
BAC
BUSY
Access Time fromChip Enable
____
25
____
35
____
45
ns
t
BDC
BUSY
Disable Time fromChip Enable
____
25
____
35
____
45
ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(3)
____
35
____
40
____
50
ns
BUSY
TIMING (M/
S
- V
IL
)
t
WB
BUSY
Input to Write
(4)
0
____
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
20
____
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
55
____
65
____
85
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
50
____
60
____
80
ns
2943 tbl 13
相關PDF資料
PDF描述
IDT70V07S35GI HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
IDT70V07L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
IDT70V07S55PF HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
IDT70V07L25G HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
IDT70V07L25J HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
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