參數(shù)資料
型號(hào)： IDT70V06S55JI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： HIGH-SPEED 3.3V 16K x 8 DUAL-PORT STATIC RAM
中文描述： 16K X 8 DUAL-PORT SRAM, 55 ns, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 19/22頁(yè)
文件大?。?/td> 171K
代理商： IDT70V06S55JI
6.42
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V06 SRAMs.
enough for a
BUSY
flag to be output fromthe master before the actual write
pulse can be initiated with the R/
W
signal. Failure to observe this timng
can result in a glitched internal write inhibit signal and corrupted data in the
slave.
.&
The IDT70V06 is an extremely fast Dual-Port 16K x 8 CMOS Static
RAMwith an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or right
side of the Dual-Port SRAMto claima privilege over the other processor
for functions defined by the systemdesigner
’
s software. As an ex-
ample, the semaphore can be used by one processor to inhibit the
other fromaccessing a portion of the Dual-Port SRAMor any other shared
resource.
The Dual-Port SRAMfeatures a fast access time, and both ports
are completely independent of each other. This means that the activity
on the left port in no way slows the access time of the right port. Both
ports are identical in function to standard CMOS Static RAMand can
be read from or written to, at the same time with the only possible
conflict arising fromthe simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
systemprogramto avoid any conflicts in the non-semaphore portion
of the Dual-Port SRAM. These devices have an automatic power-
down feature controlled by
CE
, the Dual-Port SRAMenable, and
SEM
,
the semaphore enable. The
CE
and
SEM
pins control on-chip power
down circuitry that permts the respective port to go into standby mode
when not selected. This is the condition which is shown in Truth Table
I where
CE
and
SEM
are both HIGH.
Systems which can best use the IDT70V06 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit froma performance increase offered by the IDT70V06's
hardware semaphores, which provide a lockout mechanismwithout
requiring complex programmng.
Software handshaking between processors offers the maximumin
systemflexibility by permtting shared resources to be allocated in
varying configurations. The IDT70V06 does not use its semaphore flags
allows one of the two accesses to proceed and signals the other side that
the SRAMis
“
busy
”
. The
BUSY
pin can then be used to stall the access
until the operation on the other side is completed. If a write operation has
been attempted fromthe side that receives a
BUSY
indication, the write
signal is gated internally to prevent the write fromproceeding.
The use of
BUSY
logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the
BUSY
outputs together
and use any
BUSY
indication as an interrupt source to flag the event of an
illegal or illogical operation. If the write inhibit function of BUSY logic is not
desirable, the
BUSY
logic can be disabled by placing the part in slave mode
with the M/
S
pin. Once in slave mode the
BUSY
pin operates solely as
a pin. Normal operation can be programmed by tying the
BUSY
pins HIGH.
If desired, unintended write operations can be prevented to a port by tying
the
BUSY
pin for that port LOW.
The
BUSY
outputs on the IDT 70V06 RAMin master mode, are
push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the busy indication
for the resulting array requires the use of an external AND gate.
-+&/6;&2B
,.12
When expanding an IDT70V06 SRAMarray in width while using
BUSY
logic, one master part is used to decide which side of the SRAMarray
will receive a
BUSY
indication, and to output that indication. Any number
of slaves to be addressed in the same address range as the master use
the
BUSY
signal as a write inhibit signal. Thus on the IDT70V06 RAMthe
BUSY
pin is an output if the part is used as a master (M/
S
pin = V
IH
), and
the
BUSY
pin is an input if the part used as a slave (M/
S
pin = V
IL
) as shown
in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating
BUSY
on one side
of the array and another master indicating
BUSY
on one other side of
the array. This would inhibit the write operations fromone port for part
of a word and inhibit the write operations fromthe other port for part of
the other word.
The
BUSY
arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid long
2942 drw 18
MASTER
Dual Port
SRAM
(L)
(R)
MASTER
Dual Port
SRAM
(L)
(R)
SLAVE
Dual Port
SRAM
(L)
(R)
SLAVE
Dual Port
SRAM
(L)
(R)
(L)
(R)
D
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