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參數(shù)資料
| 型號(hào)： | IDT70V06S35PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | -12V P-Channel 1.8V Specified PowerTrench MOSFET |
| 中文描述： | 16K X 8 DUAL-PORT SRAM, 35 ns, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數(shù)： | 18/22頁 |
| 文件大小： | 171K |
| 代理商： | IDT70V06S35PF |
18
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
%&%'(3@++
'
BUSY
NOTES:
1.
Pins
BUSY
L
and
BUSY
R
are both outputs when the part is configured as a master. Both are inputs when configured as a slave.
BUSY
X
outputs on the IDT70V06 are push
pull, not open drain outputs. On slaves the
BUSY
X
input internally inhibits writes.
L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after the address and enable
inputs of this port. If t
APS
is not met, either
BUSY
L
or
BUSY
R
= LOW will result.
BUSY
L
and
BUSY
R
outputs cannot be LOW simultaneously.
Writes to the left port are internally ignored when
BUSY
L
outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSY
R
outputs are driving LOW regardless of actual logic level on the pin.
2.
3.
%&%'3@/6.&.A
!
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V06.
2. There are eight semaphore flags written to via I/O
0
and read fromall I/O's (I/O
0
- I/O
7
). These eight semaphores are addressed by A
0
-A
2
.
3.
CE
= V
IH
,
SEM
= V
IL
to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
The IDT70V06 provides two ports with separate control, address
and I/O pins that permt independent access for reads or writes to any
location in memory. The IDT70V06 has an automatic power down
feature controlled by
CE
. The
CE
controls on-chip power down circuitry
that permts the respective port to go into a standby mode when not
selected (
CE
= V
IH
). When a port is enabled, access to the entire
memory array is permtted.
(
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (
INT
L
) is set when the right port writes to memory location 3FFE
(HEX). The left port clears the interrupt by reading address location 3FFE.
Likewise, the right port interrupt flag (
INT
R
) is set when the left port writes
to memory location 3FFF (HEX) and to clear the interrupt flag (
INT
R
), the
right port must read the memory location 3FFF. The message (8 bits) at
3FFE or 3FFF is user-defined. If the interrupt function is not used, address
locations 3FFE and 3FFF are not used as mail boxes, but as part of the
randomaccess memory. Refer to Truth Table III for the interrupt
operation.
2B
Busy Logic provides a hardware indication that both ports of the
SRAMhave accessed the same location at the same time. It also
Inputs
Outputs
Function
L
R
A
13L
-A
0L
A
13R
-A
0R
L
(1)
R
(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit
(3)
2942 tbl 16
Functions
D
0
- D
7
Left
D
0
- D
7
Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
2942 tbl 17
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