參數(shù)資料
型號(hào)： IDT70V06S35G
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 200V N-Channel PowerTrench MOSFET; Package: TO-252(DPAK); No of Pins: 2; Container: Tape & Reel
中文描述： 16K X 8 DUAL-PORT SRAM, 35 ns, CPGA68
封裝： CERAMIC, PGA-68
文件頁(yè)數(shù)： 21/22頁(yè)
文件大小： 171K
代理商： IDT70V06S35G
6.42
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
<.&@./6
Perhaps the simplest application of semaphores is their application as
resource markers for the IDT70V06
’
s Dual-Port SRAM. Say the 16K x
8 SRAMwas to be divided into two 8K x 8 blocks which were to be
dedicated at any one time to servicing either the left or right port. Semaphore
0 could be used to indicate the side which would control the lower section
of memory, and Semaphore 1 could be defined as the indicator for the
upper section of memory.
To take a resource, in this example the lower 8K of Dual-Port
SRAM the processor on the left port could write and then read a zero in
to Semaphore 0. If this task were successfully completed (a zero was read
back rather than a one), the left processor would assume control of the
lower 8K. Meanwhile the right processor was attempting to gain control of
the resource after the left processor, it would read back a one in response
to the zero it had attempted to write into Semaphore 0. At this point, the
software could choose to try and gain control of the second 8K section by
writing, then reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could
undo its semaphore request and performother tasks until it was able
to write, then read a zero into Semaphore 1. If the right processor
performs a simlar task with Semaphore 0, this protocol would allow the
two processors to swap 8K blocks of Dual-Port SRAMwith each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the
D
0
2942 drw 19
D
Q
WRITE
D
0
WRITE
D
Q
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
L PORT
R PORT
SEMAPHORE
READ
SEMAPHORE
READ
,
Figure 4. IDT70V06 Semaphore Logic
Dual-Port SRAMor other shared resources into eight parts. Semaphores
can even be assigned different meanings on different sides rather than
being given a common meaning as was shown in the example above.
Semaphores are a useful formof arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory
during a transfer and the I/O device cannot tolerate any wait states.
With the use of semaphores, once the two devices has determned
which memory area was
“
off-limts
”
to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continu-
ously without any wait states.
Semaphores are also useful in applications where no memory
“
WAIT
”
state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned SRAMsegments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
go in and update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting processor
to come back and read the complete data structure, thereby guaran-
teeing a consistent data structure.
相關(guān)PDF資料
PDF描述
IDT70V06S35GI 200V N-Channel PowerTrench MOSFET
IDT70V06S35J HIGH-SPEED 3.3V 16K x 8 DUAL-PORT STATIC RAM
IDT70V06S35JI -12V P-Channel 1.8V Specified PowerTrench MOSFET; Package: TO-252(DPAK); No of Pins: 2; Container: Tape &amp; Reel
IDT70V06S35PF -12V P-Channel 1.8V Specified PowerTrench MOSFET
IDT70V06S35PFI 80V Dual N &amp; P-Channel PowerTrench MOSFET; Package: TO-252(DPAK); No of Pins: 5; Container: Tape &amp; Reel
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT70V06S35J 功能描述:IC SRAM 128KBIT 35NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF
IDT70V06S35J8 功能描述:IC SRAM 128KBIT 35NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF
IDT70V06S35PF 功能描述:IC SRAM 128KBIT 35NS 64TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF
IDT70V06S35PF8 功能描述:IC SRAM 128KBIT 35NS 64TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF
IDT70V06S55G 功能描述:IC SRAM 128KBIT 55NS 68PGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8
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