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參數(shù)資料
| 型號(hào)： | IDT70V06L15G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 3.3V 16K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 16K X 8 DUAL-PORT SRAM, 15 ns, CPGA68 |
| 封裝： | CERAMIC, PGA-68 |
| 文件頁數(shù)： | 11/22頁 |
| 文件大?。?/td> | 171K |
| 代理商： | IDT70V06L15G |
6.42
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
%-1-2"$,
W
+%
8>!
%-1-2"$
CE
+%
8>!
NOTES:
1. R/
W
or
CE
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of a LOW
CE
and a LOW R/
W
for memory array writing cycle.
3. t
WR
is measured fromthe earlier of
CE
or R/
W
(or
SEM
or R/
W
) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE
or
SEM
LOW transition occurs simultaneously with or after the R/W low transition, the outputs remain in the High-impedance state.
6. Timng depends on which enable signal is asserted last,
CE
, or R/
W
.
7. Timng depends on which enable signal is de-asserted first,
CE
, or R/
W
.
8. If
OE
is LOW during R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off and data to be placed on the
bus for the required t
DW
. If
OE
is HIGH during an R/
W
controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
WP
.
9. To access SRAM
CE
= V
IL
and
SEM
= V
IH
. To access Semaphore,
CE
= V
IH
and
SEM
= V
IL
. t
EW
must be met for either condition.
R/
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
ADDRESS
DATA
IN
or
(6)
(4)
(4)
(3)
2942 drw 08
(7)
(7)
(9)
2942 drw 09
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
or
R/
t
AW
t
EW
(3)
(2)
(6)
(9)
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| IDT70V06L15JG | 功能描述:IC SRAM 128KBIT 15NS 68PLCC RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT70V06L15JG8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 128KBIT 15NS 68PLCC |
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