參數(shù)資料
型號(hào)： IDT70V05L55JI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM
中文描述： 8K X 8 DUAL-PORT SRAM, 55 ns, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 19/22頁(yè)
文件大?。?/td> 172K
代理商： IDT70V05L55JI
6.42
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
The IDT70V05 provides two ports with separate control, address
and I/O pins that permt independent access for reads or writes to any
location in memory. The IDT70V05 has an automatic power down
feature controlled by
CE
. The
CE
controls on-chip power down circuitry
that permts the respective port to go into a standby mode when not
selected (
CE
HIGH). When a port is enabled, access to the entire
memory array is permtted.
-
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (
INT
L
) is set when the right port writes to memory location 1FFE
(HEX). The left port clears the interrupt by reading address location
1FFE. Likewise, the right port interrupt flag (
INT
R
) is set when the left
port writes to memory location 1FFF (HEX) and to clear the interrupt
flag (INT
R
), the right port must read the memory location 1FFF. The
message (8 bits) at 1FFE or 1FFF is user-defined. If the interrupt
function is not used, address locations 1FFE and 1FFF are not used
as mail boxes, but as part of the randomaccess memory. Refer to
Truth Table III for the interrupt operation.
2B
Busy Logic provides a hardware indication that both ports of the
SRAMhave accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAMis
“
busy
”
. The
BUSY
pin can then be used to stall the
access until the operation on the other side is completed. If a write
operation has been attempted fromthe side that receives a
BUSY
indication, the write signal is gated internally to prevent the write from
proceeding.
The use of
BUSY
logic is not required or desirable for all applica-
tions. In some cases it may be useful to logically OR the
BUSY
outputs
together and use any
BUSY
indication as an interrupt source to flag the
event of an illegal or illogical operation. If the write inhibit function of
BUSY
logic is not desirable, the
BUSY
logic can be disabled by placing
the part in slave mode with the M/
S
pin. Once in slave mode the
BUSY
pin operates solely as a write inhibit input pin. Normal operation can be
programmed by tying the
BUSY
pins HIGH. If desired, unintended
write operations can be prevented to a port by tying the
BUSY
pin for
that port LOW.
The
BUSY
outputs on the IDT 70V05 SRAMin master mode, are
push-pull type outputs and do not require pull up resistors to
operate. If these SRAMs are being expanded in depth, then the
BUSY
indication for the resulting array requires the use of an external
AND gate.
,*&/6;&2B
+.12
When expanding an IDT70V05 SRAMarray in width while using
BUSY
logic, one master part is used to decide which side of the RAM
array will receive a
BUSY
indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master, use the
BUSY
signal as a write inhibit signal. Thus on the
IDT70V05 SRAMthe
BUSY
pin is an output if the part is used as a
master (M/
S
pin = V
IH
), and the
BUSY
pin is an input if the part used
as a slave (M/
S
pin = V
IL
) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating
BUSY
on one side
of the array and another master indicating
BUSY
on one other side of
the array. This would inhibit the write operations fromone port for part
of a word and inhibit the write operations fromthe other port for the
other part of the word.
The
BUSY
arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a
BUSY
flag to be output fromthe master before the
actual write pulse can be initiated with the R/
W
signal. Failure to
observe this timng can result in a glitched internal write inhibit signal
and corrupted data in the slave.
.&
The IDT70V05 is a fast Dual-Port 8K x 8 CMOS Static RAMwith
an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-
Port SRAMto claima privilege over the other processor for functions
defined by the systemdesigner
’
s software. As an example, the
semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port SRAMor any other shared
resource.
The Dual-Port SRAMfeatures a fast access time, and both ports are
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V05 SRAMs.
2941 drw 18
MASTER
Dual Port
SRAM
(L)
(R)
MASTER
Dual Port
SRAM
(L)
(R)
SLAVE
Dual Port
SRAM
(L)
(R)
SLAVE
Dual Port
SRAM
(L)
(R)
(L)
(R)
D
相關(guān)PDF資料
PDF描述
IDT70V05L55PFI HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM
IDT70V05S15G HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM
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IDT70V05S15J8 功能描述:IC SRAM 64KBIT 15NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF
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