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參數(shù)資料
| 型號： | IDT70T3539MS166BCI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 2.5V 512K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| 中文描述： | 高速與3.3V 2.5V的為512k × 36 SYNCHRONOU S雙，端口靜態(tài)RAM或2.5V的接口 |
| 文件頁數(shù)： | 5/26頁 |
| 文件大?。?/td> | 421K |
| 代理商： | IDT70T3539MS166BCI |
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6.42
IDT70T3539M Preliminary
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control
(1,2,3,4)
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS
,
CNTEN
,
REPEAT
= V
IH
.
3.
OE
and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
OE
CLK
CE
0
CE
1
BE
3
BE
2
BE
1
BE
0
R/
W
ZZ
Byte 3
I/O
27-35
Byte 2
I/O
18-26
Byte 1
I/O
9-17
Byte 0
I/O
0-8
MODE
X
↑
H
X
X
X
X
X
X
L
High-Z
High-Z
High-Z
High-Z
Deselected–Power Down
X
↑
X
L
X
X
X
X
X
L
High-Z
High-Z
High-Z
High-Z
Deselected–Power Down
X
↑
L
H
H
H
H
H
X
L
High-Z
High-Z
High-Z
High-Z
All Bytes Deselected
X
↑
L
H
H
H
H
L
L
L
High-Z
High-Z
High-Z
D
IN
Write to Byte 0 Only
X
↑
L
H
H
H
L
H
L
L
High-Z
High-Z
D
IN
High-Z
Write to Byte 1 Only
X
↑
L
H
H
L
H
H
L
L
High-Z
D
IN
High-Z
High-Z
Write to Byte 2 Only
X
↑
L
H
L
H
H
H
L
L
D
IN
High-Z
High-Z
High-Z
Write to Byte 3 Only
X
↑
L
H
H
H
L
L
L
L
High-Z
High-Z
D
IN
D
IN
Write to Lower 2 Bytes Only
X
↑
L
H
L
L
H
H
L
L
D
IN
D
IN
High-Z
High-Z
Write to Upper 2 bytes Only
X
↑
L
H
L
L
L
L
L
L
D
IN
D
IN
D
IN
D
IN
Write to All Bytes
L
↑
L
H
H
H
H
L
H
L
High-Z
High-Z
High-Z
D
OUT
Read Byte 0 Only
L
↑
L
H
H
H
L
H
H
L
High-Z
High-Z
D
OUT
High-Z
Read Byte 1 Only
L
↑
L
H
H
L
H
H
H
L
High-Z
D
OUT
High-Z
High-Z
Read Byte 2 Only
L
↑
L
H
L
H
H
H
H
L
D
OUT
High-Z
High-Z
High-Z
Read Byte 3 Only
L
↑
L
H
H
H
L
L
H
L
High-Z
High-Z
D
OUT
D
OUT
Read Lower 2 Bytes Only
L
↑
L
H
L
L
H
H
H
L
D
OUT
D
OUT
High-Z
High-Z
Read Upper 2 Bytes Only
L
↑
L
H
L
L
L
L
H
L
D
OUT
D
OUT
D
OUT
D
OUT
Read All Bytes
H
↑
X
X
X
X
X
X
X
L
High-Z
High-Z
High-Z
High-Z
Outputs Disabled
X
X
X
X
X
X
X
X
X
H
High-Z
High-Z
High-Z
High-Z
Sleep Mode
5678 tbl 02
Truth Table II—Address Counter Control
(1,2)
Previous
Internal
Address
Used
CLK
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/
W
,
CE
0
, CE
1
,
BE
n and
OE
.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4.
ADS
and
REPEAT
are independent of all other memory control signals including
CE
0
, CE
1
and
BE
n
5. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other memory control signals including
CE
0
, CE
1
,
BE
n.
6. When
REPEAT
is asserted, the counter will reset to the last valid address loaded via
ADS
. This value is not set at power-up: a known location should be loaded
via
ADS
during initialization if desired. Any subsequent
ADS
access during operations will update the
REPEAT
address location.
Address
Internal
Address
ADS
CNTEN
REPEAT
(6)
I/O
(3)
MODE
An
X
An
↑
L
(4)
X
H
D
I/O
(n)
External Address Used
X
An
An + 1
↑
H
L
(5)
H
D
I/O
(n+1)
Counter Enabled—Internal Address generation
X
An + 1
An + 1
↑
H
H
H
D
I/O
(n+1)
External Address Blocked—Counter disabled (An + 1 reused)
X
X
An
↑
X
X
L
(4)
D
I/O
(n)
Counter Set to last valid
ADS
load
5678 tbl 03
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