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參數(shù)資料
| 型號： | IDT70M74S45GB |
| 英文描述： | Quad-Port SRAM Module |
| 中文描述： | 四端口SRAM模塊 |
| 文件頁數(shù)： | 3/15頁 |
| 文件大小： | 190K |
| 代理商： | IDT70M74S45GB |
6.42
IDT70V9379L
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
11
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3.
CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since
ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
R/W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
DATAIN
Dn + 2
CE0
CLK
4857 drw 12
Qn
DATAOUT
CE1
UB, LB
tCD1
Qn + 1
tCH1
tCL1
tCYC1
tSD tHD
tCD1
tDC
tCKHZ
Qn + 3
tCD1
tDC
tSC
tHC
tSB
tHB
tSW tHW
tSA
tHA
READ
NOP
READ
tCKLZ
(4)
(2)
(1)
tSW tHW
WRITE
(5)
R/W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
An + 5
(4)
DATAIN
Dn + 2
CE0
CLK
4857 drw 13
Qn
DATAOUT
CE1
UB, LB
tCD1
tCH1
tCL1
tCYC1
tSD tHD
tCD1
tDC
Qn + 4
tCD1
tDC
tSC
tHC
tSB
tHB
tSW tHW
tSA
tHA
READ
WRITE
READ
tCKLZ
(2)
Dn + 3
tOHZ
(1)
tSW tHW
OE
tOE
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