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參數(shù)資料
| 型號： | IDT7099S |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | JFET-Input Operational Amplifier 8-PDIP 0 to 70 |
| 中文描述： | 高速4K的× 9同步雙端口RAM |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 131K |
| 代理商： | IDT7099S |
6.23
8
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE I – READ/WRITE CONTROL
(1)
Inputs
Synchronous
(3)
Asynchronous
CLK
CE
Byte R/
W
h
h
h
l
h
h
h
l
l
l
l
l
l
h
l
h
l
l
l
h
l
h
l
h
l
h
Outputs
I/O0-7
High-Z
DATA
IN
High-Z
DATA
IN
DATA
IN
DATA
OUT
DATA
IN
DATA
OUT
DATA
IN
High-Z
DATA
IN
DATA
OUT
DATA
OUT
High-Z
DATA
OUT
High-Z
Bit R/
h
h
l
l
h
h
l
l
l
h
h
h
h
W
Byte
X
X
X
X
X
X
L
H
X
L
H
L
H
OE
Bit
X
X
X
X
L
H
X
X
X
L
L
H
H
OE
I/O8
High-Z
High-Z
DATA
IN
DATA
IN
Mode
Deselected, Power Down, Data I/O Disabled
Deselected, Power Down, Byte Data Input Enabled
Deselected, Power Down, Bit Data Input Enabled
Deselected, Power Down, Data Input Enabled
Write Byte, Read Bit
Write Byte Only
Read Byte, Write Bit
Write Bit Only
Write Byte, Write Bit
Read Byte, Read Bit
Read Bit Only
Read Byte Only
Data I/O Disabled
High-Z
DATA
IN
DATA
IN
DATA
OU
T
High-Z
High-Z
3007 tbl 09
FUNCTIONAL DESCRIPTION
The IDT7099 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide very short set-up
and hold times on address, data, and all critical control inputs.
All internal registers are clocked on the rising edge of the clock
signal. An asynchronous output enable is provided to ease
asynchronous bus interfacing.
The internal write pulse width is dependent on the low to
high transitions of the clock signal allowing the shortest
possible realized cycle times. Clock enable inputs are
provided to stall the operation of the address and data input
registers without introducing clock skew for very fast inter-
leaved memory applications.
The data inputs are gated to control on-chip noise in bussed
applications. The user must guarantee that the BYTE R/
W
and
BIT R/
W
pins are low for at least one clock cycle before any
write is attempted. A High on the
CE
input for one clock cycle
will power down the internal circuitry to reduce static power
consumption.
The device has separate Bit Write, Byte Write, Bit Enable,
and Byte Enable pins to allow for independent control.
TRUTH TABLE II – CLOCK ENABLE FUNCTION TABLE
(1)
Inputs
Register Inputs
Register Outputs
Operating Mode
Load "1"
Load "0"
Hold (do nothing)
CLK
(3)
CLKEN
(2)
ADDR
h
l
X
X
DATAIN
h
l
X
X
ADDR
H
L
NC
NC
DATAOUT
H
L
NC
NC
l
l
h
H
X
NOTES:
1. 'H' = High voltage level steady state, 'h' = High voltage level one set-up time prior to the low-to-high clock transition, 'L' = Low voltage level steady state
'l' = Low voltage level one set-up time prior to the Low-to-High clock transition, 'X' = Don't care, 'NC' = No change
2.
CLKEN
= V
IL
must be clocked in during Power-Up.
3. Control signals are initialted and terminated on the rising edge of the CLK, depending on their input level. When R/
W
and
CE
are low, a write cycle is initiated
on the low-to-high transition of the CLK. Termination of a write cycle is done on the next low-to-high transistion of the CLK.
3007 tbl 10
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