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參數(shù)資料
| 型號： | IDT7099S25PFB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | JFET-Input Operational Amplifier 8-SOIC 0 to 70 |
| 中文描述： | 高速4K的× 9同步雙端口RAM |
| 文件頁數(shù)： | 7/9頁 |
| 文件大小： | 131K |
| 代理商： | IDT7099S25PFB |
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.23
7
TIMING WAVEFORM OF READ-TO-WRITE CYCLE NO. 1,
CE
= V
IH
(2)
TIMING WAVEFORM OF READ-TO-WRITE CYCLE NO. 2,
CE
= V
IL
(2)
NOTES:
1. During dead cycle, if
CE
= V
IL
, then invalid data will be written into array. The An+1 must be rewritten on the following cycle.
2.
OE
low throughout.
3. Transition is measured +/-200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
BYTE R/
W
or BIT R/
W
ADDRESS
DATA
IN
CE
CLKEN
CLK
3007 drw 10
An
An + 1
An + 3
t
CYC
t
CH
t
CL
t
H
t
CKLZ
t
CYC
t
CH
t
CL
t
S
Dn + 3
Qn
t
CD
t
CKHZ
DATA
OUT
(3)
(3)
An + 2
Dn + 2
BYTE R/
W
or BIT R/
W
ADDRESS
DATA
IN
CE
CLKEN
CLK
3007 drw 11
An
An + 1
An + 1
An + 2
t
CYC
t
CH
t
CL
t
H
t
CKLZ
t
CYC
t
CH
t
CL
t
S
Dn + 1
Dn + 2
Qn
t
CD
t
CKHZ
DATA
OUT
(3)
(3)
(1)
(1)
(1)
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