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參數資料
| 型號： | IDT7099S20PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | JFET-Input Operational Amplifier 8-PDIP -40 to 85 |
| 中文描述： | 4K X 9 MULTI-PORT SRAM, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數： | 6/9頁 |
| 文件大?。?/td> | 131K |
| 代理商： | IDT7099S20PF |
6.23
6
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
An
An + 1
An + 2
An + 3
t
CYC
t
CH
t
CL
t
SCK
t
HCK
t
SCK
BYTE R/
W
or BIT R/
W
ADDRESS
DATA
OUT
CE
CLKEN
CLK
BYTE
OE
or BIT
OE
t
S
t
H
t
CD
t
DC
t
CKLZ
Qn
Qn + 1
Qn + 1
t
OHZ
t
OLZ
t
OE
t
CKHZ
3007 drw 08
(1)
(1)
(1)
(1)
TIMING WAVEFORM OF READ CYCLE, EITHER SIDE
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ
(1,2,3)
NOTE:
1. Transition is measured +/-200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
DATA
IN
"A"
CLK
"B"
R/
W
"B"
ADDR
"A"
R/
W
"A"
CLK
"A"
ADDR
"B"
NO
MATCH
MATCH
NO
MATCH
MATCH
VALID
t
CWDD
t
CD
t
DC
DATA
OUT
"B"
3007 drw 09
VALID
VALID
(4)
NOTES:
1.
CE
L =
CE
R
= V
IL
,
CLKEN
L
=
CLKEN
R
= V
IL
2.
OE
= V
IL
for the reading port, port 'B'.
3. All timing is the same for left and right ports. Ports "A" may be either the left or right port. Port "B" is opposite from port "A".
4. R/
W
'A'
was active (V
IL
) during the previous CLK
'A',
when enabled the write path.
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