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| 型號(hào)： | IDT7099S20G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | JFET-Input Operational Amplifier 8-SOIC -40 to 85 |
| 中文描述： | 4K X 9 MULTI-PORT SRAM, CPGA68 |
| 封裝： | CAVITY UP, PGA-68 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 131K |
| 代理商： | IDT7099S20G |
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.23
5
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE RANGE —
(READ AND WRITE CYCLE TIMING)
(Commercial: V
CC
= 5V
±
10%, T
A
= 0
°
C to +70
°
C; Military: V
CC
= 5V
±
10%, T
A
= -55
°
C to +125
°
C)
Commercial
7099S15
7099S20
Symbol
Parameter
Min. Max. Min.
t
CYC
Clock Cycle Time
20
—
20
t
CH
Clock High Time
6
—
8
t
CL
Clock Low Time
6
—
8
t
CD
Clock High to Output Valid
—
15
—
t
S
Registered Signal Set-up Time
4
—
5
t
H
Registered Signal Hold Time
1
—
1
t
DC
Data Output Hold After Clock High
3
—
3
t
CKLZ
Clock High to Output Low-Z
(1,2)
2
—
2
t
CKHZ
Clock High to Output High-Z
(1,2)
—
7
—
t
OE
Output Enable to Output Valid
—
8
—
t
OLZ
Output Enable to Output Low-Z
(1,2)
0
—
0
t
OHZ
Output Disable to Output High-Z
(1,2)
—
7
—
t
SCK
Clock Enable, Disable Set-up Time
4
—
5
t
HCK
Clock Enable, Disable Hold Time
2
—
2
Port-to-Port Delay
t
CWDD
Write Port Clock High to Read
—
30
—
Data Delay
Military
7099S25
7099S25
Min. Max.
25
10
10
—
6
1
3
2
—
—
0
—
6
2
7099S20
Min. Max. Min. Max. Min. Max.
20
—
25
8
—
10
8
—
10
—
20
—
5
—
6
2
—
2
3
—
3
2
—
2
—
9
—
—
10
—
0
—
0
—
9
—
5
—
6
3
—
3
7099S30
Max.
—
—
—
20
—
—
—
—
9
10
—
9
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
25
—
—
—
—
12
12
—
11
—
—
—
—
—
25
—
—
—
—
12
12
—
11
—
—
30
12
12
—
7
2
3
2
—
—
0
—
7
3
—
—
—
30
—
—
—
—
15
15
—
14
—
—
35
—
45
—
35
—
45
—
55
ns
3007 tbl 08
1
2
3
4
5
6
7
8
20 40
100
60 80
Capacitance (pF)
120 140 160 180 200
tCD
(Typical, ns)
3007 drw 07
-1
0
- 10pF is the I/O capacitance
of this device, and 3pF is the
AC Test Load Capacitance
Figure 3. Typical Output Derating (Lumped Capacitive Load).
893
30pF
347
5V
DATA
OUT
893
5pF
347
5V
DATA
OUT
Figure 1. AC Output Test load.
Figure 2. Output Test Load
(For t
CLZ
, t
CHZ
, t
OLZ
, and t
OHZ
).
Including scope and jig.
NOTES:
1. Transition is measured +/-200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
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