參數(shù)資料
型號(hào): IDT709289L9PFI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 64K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
中文描述: 64K X 16 DUAL-PORT SRAM, 20 ns, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
文件頁(yè)數(shù): 13/15頁(yè)
文件大?。?/td> 190K
代理商: IDT709289L9PFI
6.42
IDT709289L
High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges
13
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NOTES:
1.
CE
0
,
UB
,
LB
, and R/
W
= V
IL
; CE
1
and
CNTRST
= V
IH
.
2.
CE
0
,
UB
,
LB
= V
IL
; CE
1
= V
IH
.
3. The "Internal Address" is equal to the "External Address" when
ADS
= V
IL
and equals the counter output when
ADS
= V
IH
.
4. Addresses do not have to be accessed sequentially since
ADS
= V
IL
constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determned by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle.
7.
CNTEN
= V
IL
advances Internal Address from
An
to
An +1
. The transition shown indicates the time required for the counter to advance. The
An +1
Address is written
to during this cycle.
ADDRESS
An
CLK
DATA
IN
Dn
Dn + 1
Dn + 1
Dn + 2
ADS
CNTEN
t
CH2
t
CL2
t
CYC2
4842 drw 17
INTERNAL
(3)
ADDRESS
An
(7)
An + 1
An + 2
An + 3
An + 4
Dn + 3
Dn + 4
t
SA
t
HA
t
SAD
t
HAD
WRITE
COUNTER HOLD
WRITE WITH COUNTER
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
t
SD
t
HD
ADDRESS
An
D
0
t
CH2
t
CL2
t
CYC2
Q
0
Q
1
0
CLK
DATA
IN
R/
W
CNTRST
4842 drw 18
INTERNAL
(3)
ADDRESS
ADS
CNTEN
t
SRST
t
HRST
t
SD
t
HD
t
SW
t
HW
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
Qn
An + 1
An + 2
READ
ADDRESS n+1
DATA
OUT
t
SA
t
HA
1
An
An + 1
(5)
(6)
Ax
(4)
(6)
.
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