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| 型號： | IDT70825S |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | High Speed Low-Noise JFET-Input Dual Operational Amplifier 8-CDIP -55 to 125 |
| 中文描述： | 高速8K的× 16順序訪問隨機(jī)存取存儲器（單存取RAM⑩） |
| 文件頁數(shù)： | 3/21頁 |
| 文件大小： | 319K |
| 代理商： | IDT70825S |
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.31
3
SYMBOL
SI/O0-15 Inputs
SCLK
NAME
I/O
(1)
I/O
I
DESCRIPTION
Sequential data inputs/outputs for 16-bit wide data.
SI/
O0
-SI/
O15
,
SCE
, SR/
W
, and
SLD
are registered on the LOW-to-HIGH transition of SCLK.
Also, the sequential access port address pointer increments by 1 on each LOW-to-HIGH
transition of SCLK when
CNTEN
is LOW.
When
SCE
is LOW, the sequential access port is enabled on the LOW-to-HIGH transition of
SCLK. When
SCE
is HIGH, the sequential access port is disabled into powered-down mode on
the LOW-to-HIGH transition of SCLK, and the SI/O outputs are in the high-impedance state. All
data is retained, unless altered by the random access port.
When
CNTEN
is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK.
This function is independant of
SCE
.
When SR/
W
and
SCE
are LOW, a write cycle is initiated on the LOW-to-HIGH transition of
SCLK. When SR/
W
is HIGH, and
SCE
and
SOE
are LOW, a read cycle is initiated on the
LOW-to-HIGH transition of SCLK. Termination of a Write cycle is done on the Low-to-High
transistion of SCLK if SR/
W
or
SCE
is High.
When
SLD
is sampled LOW, there is an internal delay of one cycle before the address pointer
changes. When
SLD
is LOW, data on the inputs SI/
O0
-SI/
O11
is loaded into a data-in register
on the LOW-to-HIGH transition of SCLK. On the cycle following
SLD
, the address pointer
changes to the address location contained in the data-in register.
SSTRT
1
and
SSTRT
2
may
not be LOW while
SLD
is LOW or during the cycle following
SLD
.
When
SSTRT
1
or
SSTRT
2
is LOW, the start of address register #1 or #2 is loaded into the
address pointer on the LOW-to-HIGH transition of SCLK. The start addresses are stored in
internal registers.
SSTRT
1
and
SSTRT
2
may not be LOW while
SLD
is LOW or during the cycle
following
SLD
.
EOB
1
or
EOB
2
is output LOW when the address pointer is incremented to match the address
stored in the end of buffer registers. The flags can be cleared by either asserting
RST
LOW or
by writing zero into bit 0 and/or bit 1 of the control register at address 101.
EOB
1
and
EOB
2
are
dependent on separate internal registers, and therefore separate match addresses.
SOE
controls the data outputs and is independent of SCLK. When
SOE
is LOW, output buffers
and the sequentially addressed data is output. When
SOE
is HIGH, the SI/O output bus is in
the high-impedance state.
SOE
is asynchronous to SCLK.
When
RST
is LOW, all internal registers are set to their default state, the address pointer is set
to zero and the
EOB
1
and
EOB
2
flags are set HIGH.
RST
is asynchronous to SCLK.
Clock
SCE
Chip Enable
I
CNTEN
Counter Enable
I
SR/
W
Read/Write Enable
I
SLD
Address Pointer
Load Control
I
SSTRT
1,
SSTRT
2
Load Start of
Address Register
I
EOB
1,
EOB
2
End of Buffer Flag
O
SOE
Output Enable
I
RST
Reset
I
3016 tbl 02
SYMBOL
A
0
-A
12
I/
O0
-I/
O15
Inputs/Outputs
CE
Chip Enable
NAME
Address Lines
I/O
(1)
I
I
I
DESCRIPTION
Address inputs to access the 8192-word (16 bit) memory array.
Random access data inputs/outputs for 16-bit wide data.
When
CE
is LOW, the random access port is enabled. When
CE
is HIGH, the random access
port is disabled into power-down mode and the I/O outputs are in the high-impedance state. All
data is retained during
CE
= VIH, unless it is altered by the sequential port.
CE
and
CMD
may not
be LOW at the same time.
When
CMD
is LOW, Address lines A
0
-A
2
, R/
W
, and inputs/outputs I/
O0
-I/
O11
, are used to
access the control register, the flag register, and the start and end of buffer registers.
CMD
and
CE
may not be LOW at the same time.
If
CE
is LOW and
CMD
is HIGH, data is written into the array when R/
W
is LOW and read out of the
array when R/
W
is HIGH. If
CE
is HIGH and
CMD
is LOW, R/
W
is used to access the buffer com-
mand registers.
CE
and
CMD
may not be LOW at the same time.
When
OE
is LOW and R/
W
is HIGH, I/O0-I/O15 outputs are enabled. When
OE
is HIGH, the I/O
outputs are in the high-impedance state.
When
LB
is LOW, I/O0-I/O7 are accessible for read and write operations. When
LB
is HIGH, I/
O0
-
I/
O7
are tri-stated and blocked during read and write operations.
UB
controls access for I/O8-
I/
O15
in the same manner and is asynchronous from
LB
.
Seven +5V power supply pins. All Vcc pins must be connected to the same +5V V
CC
supply.
Ten Ground pins. All Ground pins must be connected to the same Ground supply.
CMD
Control Register
Enable
I
R/
W
Read/Write Enable
I
OE
Output Enable
I
LB
,
UB
Lower Byte, Upper
Byte Enables
I
V
CC
GND
Power Supply
Ground
3016 tbl 01
PIN DESCRIPTIONS: RANDOM ACCESS PORT
PIN DESCRIPTIONS: SEQUENTIAL ACCESS PORT
NOTE:
1. "I/O" is bidirectional Input and Output. "I" is Input and "O" is Output.
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