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| 型號(hào)： | IDT70825L25PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | High Speed Low-Noise JFET-Input Dual Operational Amplifier 20-LCCC -55 to 125 |
| 中文描述： | 8K X 16 STANDARD SRAM, 25 ns, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁(yè)數(shù)： | 8/21頁(yè) |
| 文件大小： | 319K |
| 代理商： | IDT70825L25PF |
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6.31
8
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE IV – SEQUENTIAL ADDRESS POINTER OPERATIONS
(1,2,3,4,5)
Inputs/Outputs
SLD SSTRT
1
H
L
H
H
L
H
SCLK
SSTRT
2
H
L
H
SOE
MODE
X
X
Start address for Buffer #1 loaded into Address Pointer.
Start address for Buffer #2 loaded into Address Pointer.
Data on SI/O
0
-SI/O
12
loaded into Address Pointer.
H
(6)
NOTES:
1. H = V
IH
, L = V
IL
, X = Don't Care, and High-Z = High-impedance.
2.
RST
is continuously HIGH. The conditions of
SCE
,
CNTEN
, and SR/
W
are unrelated to the sequential address pointer operations.
3.
CE
,
OE
, R/
W
,
LB
,
UB
, and I/O
0
-I/O
15
are unrelated to the sequential port control and operation, except for
CMD
which must not be used concurrently with
the sequential port operation (due to the counter and register control).
CMD
should be HIGH (CMD = V
IH
) during sequential port access.
4. Address pointer can also change when it reaches an end of buffer address. See Flow Control Bits table.
5. When
SLD
is sampled LOW, there is an internal delay of one cycle before the address pointer changes. The state of
CNTEN
is ignored and the address
is not incremented during the two cycles.
6.
SOE
may be LOW with
SCE
deselect or in the write mode using SR/
W
.
3016 tbl 14
ADDRESS POINTER LOAD CONTROL (SLD)
In
SLD
mode, there is an internal delay of one cycle before
the address pointer changes in the cycle following
SLD
. When
SLD
is LOW, data on the inputs SI/O
0
-SI/O
12
is loaded into a
data-in register on the LOW-to-HIGH transition of
SCLK
. On
the cycle following
SLD
, the address pointer changes to the
address location contained in the data-in register.
SSTRT
1
,
SSTRT
2
may not be low while
SLD
is LOW, or during the cycle
following
SLD
. The
SSTRT
1
and
SSTRT
2
require only one
clock cycle, since these addresses are pre-loaded in the
registers already.
NOTE:
1. At SCLK edge (A), SI/O
0
-SI/O
12
data is loaded into a data-in register. At edge (B), contents of the data-in register are loaded into the address pointer (i.e.
address pointer changes). At SCLK edge (A),
SSTRT
1
and
SSTRT
2
must be high to ensure for proper sequential address pointer loading. At SCLK edge
(B),
SLD
and
SSTRT
1,2
must be high to ensure for proper sequential address pointer loading. For
SSTRT
1
or
SSTRT
2
, the data to be read will be ready
for edge (B), while data will not be ready at edge (B) when
SLD
is used, but will be ready at edge (C).
SEQUENTIAL LOAD OF ADDRESS INTO POINTER/COUNTER
(1)
15
H
H
MSB
LSB SI/O BITS
3016 drw 09
H
H
12 ------------------------------------------------------------------------------------------------------------
Address Loaded into Pointer
0
14
13
NOTE:
1. "H" = V
IH
for the SI/O intput state.
SLD
SCLK
SI/O
0-11
SSTRT
1,2
A
B
ADDR
IN
3016 drw 08
C
DATA
OUT
(1)
SLD
MODE
(1)
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