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參數(shù)資料
| 型號(hào)： | IDT7034L20PF8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 4K X 18 DUAL-PORT SRAM, 20 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 167K |
| 代理商： | IDT7034L20PF8 |
6.42
IDT7034S/L
High-Speed 4K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
15
FUNCTIONAL DESCRIPTION
The IDT7034 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT7034 has an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into a standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
INTERRUPTS
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (
INTL) is asserted when the right port writes to memory location
FFE (HEX), where a write is defined as the
CER = R/WR= VIL per Truth
Table III. The left port clears the interrupt by an address location FFE
access when
CEL = OEL = VIL, R/WL is a "don't care". Likewise, the
right port interrupt flag (
INTR) is asserted when the left port writes to
memory location FFF (HEX) and to clear the interrupt flag (
INTR), the
right port must access the memory location FFF. The message (18
bits) at FFE or FFF is user-defined, since it is an addressable SRAM
location. If the interrupt function is not used, address locations FFE
and FFF are not used as mail boxes, but as part of the random access
memory. Refer to Table III for the interrupt operation.
Truth Table V Example of Semaphore Procurement Sequence(1,2,3)
NOTES:
1.
This table denotes a sequence of events for only one of the eight semaphores on the IDT7034.
2. There are eight semaphore flags written to via I/O0 and read from all I/0's. These eight semaphores are addressed by A0 - A2.
3.
CE = VIH, SEM = VIL to access the semaphores. Refer to the semaphore Read/Write Control Truth Table.
Truth Table IV Address BUSY
Arbitration
NOTES:
1.
Pins BUSYL and BUSYR are both outputs when the part is configured as a master.
BUSY are inputs when configured as a slave. BUSYx outputs on the IDT7034 are push
pull, not open drain outputs. On slaves the
BUSY asserted internally inhibits write.
2.
"L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either
BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3.
Writes to the left port are internally ignored when
BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Inputs
Outputs
Function
CEL
CER
AOL-A11L
AOR-A11R
BUSYL(1)
BUSYR(1)
X
NO MATCH
H
Normal
H
X
MATCH
H
Normal
X
H
MATCH
H
Normal
LL
MATCH
(2)
Write Inhibit(3)
4089 tbl 17
Functions
D0 - D17 Left
D0 - D17 Right
Status
No Action
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
Semaphore free
4089 tbl 18
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| IDT7034L20PFI | 功能描述:IC SRAM 72KBIT 20NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT7034L20PFI8 | 功能描述:IC SRAM 72KBIT 20NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT7034S15PF | 功能描述:IC SRAM 72KBIT 15NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
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