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參數(shù)資料
| 型號： | IDT7024 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM |
| 中文描述： | 高速4K的× 16 DUAL-PORT靜態(tài)RAM |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 292K |
| 代理商： | IDT7024 |
6.15
10
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/
W
CONTROLLED TIMING
(1,5,8)
TIMING WAVEFORM OF WRITE CYCLE NO. 2,
CE
,
UB
,
LB
CONTROLLED TIMING
(1,5)
2740 drw 10
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/
W
t
AW
t
EW
UB
or
LB
(3)
(2)
(6)
CE
or
SEM
(9)
(9)
R/
W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
(6)
(4)
(4)
(7)
UB
or
LB
2740 drw 09
(9)
CE
or
SEM
(9)
(7)
(3)
NOTES:
1. R/
W
or
CE
or
UB
&
LB
must be High during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of a Low
UB
or
LB
and a Low
CE
and a Low R/
W
for memory array writing cycle.
3. t
WR
is measured from the earlier of
CE
or R/
W
(or
SEM
or R/
W
) going High to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE
or
SEM
Low transition occurs simultaneously with or after the R/
W
Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last,
CE
, R/
W
,
UB,
or
LB
.
7. This parameter is guaranted by device characterization, but is not production tested. Transition is measured +/- 500mV steady state with the Output Test
Load (Figure 2).
8. If
OE
is Low during R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
for (t
WZ
+ t
DW
) to allow the I/O drivers to turn off and data
to be placed on the bus for the required t
DW
. If
OE
is High during an R/
W
controlled write cycle, this requirement does not apply and the write pulse
can be as short as the specified t
WP
.
9. To access RAM,
CE
= V
IL
,
UB
or
LB
= V
IL
, and
SEM
= V
IH
. To access Semaphore,
CE
= V
IH
or
UB
&
LB
= V
IH
, and
SEM
= V
IL
. t
EW
must be
met for either condition.
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| IDT7024L15JG | 功能描述:IC SRAM 64KBIT 15NS 84PLCC RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT7024L15JG8 | 功能描述:IC SRAM 64KBIT 15NS 84PLCC RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
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