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| 型號： | IDT7015S12JI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
| 中文描述： | 高速8K的× 9雙端口靜態(tài)RAM |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 178K |
| 代理商： | IDT7015S12JI |
6.42
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
AC Elec tric al Charac teristic s Over the
Operating Temperature and S upply Voltage Range
(6)
12
APRIL 04, 2006
NOTES:
1. Port-to-port delay through RAMcells fromwriting port to reading port, refer to "Timng Wave formof Write with Port-to-Port Read and
BUSY
(M/
S
= V
IH
)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
– t
WP
(actual) or t
DDD
– t
DW
(actual).
4. To ensure that the write cycle is inhibited on Port "B" during contention on Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention on Port "A".
6. 'X' in part numbers indicates power rating (S or L).
7015X12
Com'l Only
7015X15
Com'l Only
7015X17
Com'l Only
Symbol
Parameter
Mn.
Max.
Min.
Max.
Mn.
Max.
Unit
BUSY
TIMING (M/
S
= V
IH
)
t
BAA
BUSY
Access Time fromAddress
____
12
____
15
____
17
ns
t
BDA
BUSY
Disable Time fromAddress
____
12
____
15
____
17
ns
t
BAC
BUSY
Access Time fromChip Enable
____
12
____
15
____
17
ns
t
BDC
BUSY
Disable Time fromChip Enable
____
12
____
15
____
17
ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(3)
____
15
____
18
____
18
ns
t
WH
Write Hold After
BUSY
(5)
11
____
13
____
13
____
ns
BUSY
INPUT TIMING (M/
S
= V
IL
)
t
WB
BUSY
Input to Write
(4)
0
____
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
11
____
13
____
13
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
25
____
30
____
40
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
20
____
25
____
35
ns
2954 tbl 14a
7015X20
Com'l, Ind
& Mlitary
7015X25
Com'l &
Mlitary
7015X35
Com'l &
Mlitary
Symbol
Parameter
Mn.
Max.
Min.
Max.
Mn.
Max.
Unit
BUSY
TIMING (M/
S
= V
IH
)
t
BAA
BUSY
Access Time fromAddress
____
20
____
20
____
20
ns
t
BDA
BUSY
Disable Time fromAddress
____
20
____
20
____
20
ns
t
BAC
BUSY
Access Time fromChip Enable
____
20
____
20
____
20
ns
t
BDC
BUSY
Disable Time fromChip Enable
____
17
____
17
____
20
ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(3)
____
30
____
30
____
35
ns
t
WH
Write Hold After
BUSY
(5)
15
____
17
____
25
____
ns
BUSY
INPUT TIMING (M/
S
= V
IL
)
t
WB
BUSY
Input to Write
(4)
0
____
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
15
____
17
____
25
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
45
____
50
____
60
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
30
____
35
____
45
ns
2954 tbl 14b
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| IDT7015S12PF | 功能描述:IC SRAM 72KBIT 12NS 80TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT7015S12PF8 | 功能描述:IC SRAM 72KBIT 12NS 80TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT7015S12PFB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
| IDT7015S12PFI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
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