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參數(shù)資料
| 型號(hào)： | IDT7015S12GI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
| 中文描述： | 高速8K的× 9雙端口靜態(tài)RAM |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 178K |
| 代理商： | IDT7015S12GI |
6.42
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Truth Table IV — Address
BUSY
Arbitration
16
APRIL 04, 2006
NOTES:
1. Pins
BUSY
L
and
BUSY
R
are both outputs when the part is configured as a master. Both are inputs when configured as a slave.
BUSY
X
outputs on the IDT7015 are
push-pull, not open drain outputs. On slaves the
BUSY
X
input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t
APS
is not met, either
BUSY
L
or
BUSY
R
= LOW will result.
BUSY
L
and
BUSY
R
outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when
BUSY
L
outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when
BUSY
R
outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Proc urement Sequenc e
(1,2,3)
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7015.
2. There are eight semaphore flags written to via I/O
0
and read fromall I/O
s
(I/O
0
- I/O
8
). These eight semaphores are addressed by A
0
- A
2
.
3.
CE
= V
IH
,
SEM
= V
IL
to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT7015 provides two ports with separate control, address and
I/O pins that permt independent access for reads or writes to any location
in memory. The IDT7015 has an automatic power down feature controlled
by
CE
. The
CE
controls on-chip power down circuitry that permts the
respective port to go into a standby mode when not selected (
CE
HIGH).
When a port is enabled, access to the entire memory array is permtted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(
INT
L
) is asserted when the right port writes to memory location 1FFE
where a write is defined as the
CE
=
R/
W
=
V
IL
per Truth Table III. The
left port clears the interrupt by an address location 1FFE access when
CE
R
=
OE
R
=V
IL
, R/
W
is a "don't care". Likewise, the right port interrupt flag
(INT
R
) is asserted when the left port writes to memory location 1FFF and
to clear the interrupt flag (
INT
R
), the right port must access memory location
1FFF. The message (9 bits) at 1FFE or 1FFF isuser-defined since it is
an addressable SRAMlocation. If the interrupt function is not used, address
locations 1FFE and 1FFF are not used as mail boxes but are still part
of the randomaccess memory. Refer to Table III for the interrupt
operation.
Inputs
Outputs
Function
CE
L
CE
R
A
OL
-A
12L
A
OR
-A
12R
BUSY
L
(1)
BUSY
R
(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit
(3)
2954 tbl 17
Functions
D
0
- D
15
Left
D
0
- D
15
Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
2954 tbl 18
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| IDT7015S12J | 功能描述:IC SRAM 72KBIT 12NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT7015S12J8 | 功能描述:IC SRAM 72KBIT 12NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT7015S12JB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
| IDT7015S12JI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
| IDT7015S12PF | 功能描述:IC SRAM 72KBIT 12NS 80TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
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