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參數(shù)資料
| 型號(hào)： | IDT7012L45P |
| 英文描述： | x9 Dual-Port SRAM |
| 中文描述： | X9熱賣(mài)雙端口SRAM |
| 文件頁(yè)數(shù)： | 6/15頁(yè) |
| 文件大小： | 190K |
| 代理商： | IDT7012L45P |
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6.42
IDT70V9379L
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
14
Depth and Width Expansion
The IDT70V9379 features dual chip enables (refer to Truth Table I)
inordertofacilitaterapidandsimpledepthexpansionwithnorequirements
for external logic. Figure 4 illustrates how to control the varioius chip
enables in order to expand two devices in depth.
TheIDT70V9379canalsobeusedinapplicationsrequiringexpanded
width, as indicated in Figure 4. Since the banks are allocated at the
discretionoftheuser,theexternalcontrollercanbesetuptodrivetheinput
signals for the various devices as required to allow for 36-bit or wider
applications.
4857 drw 18
IDT70V9379
CE0
CE1
CE0
CE1
A15
CE1
CE0
VCC
IDT70V9379
Control Inputs
CNTRST
CLK
ADS
CNTEN
R/
W
LB, UB
OE
Figure 4. Depth and Width Expansion with IDT70V9379
Functional Description
The IDT70V9379 provides a true synchronous Dual-Port Static RAM
interface. Registered inputs provide minimal set-up and hold times on
address,data,andallcriticalcontrolinputs.Allinternalregistersareclocked
ontherisingedgeoftheclocksignal,however,theself-timedinternalwrite
pulse is independent of the LOW to HIGH transition of the clock signal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to staff the
operationoftheaddresscountersforfastinterleavedmemoryapplications.
CE0 = VIL and CE1 = VIH for one clock cycle will power down the
internalcircuitrytoreducestaticpowerconsumption.Multiplechipenables
allow easier banking of multiple IDT70V9379's for depth expansion
configurations.WhenthePipelinedoutputmodeisenabled,twocyclesare
required with
CE0 = VIL and CE1 = VIH to re-activate the outputs.
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| IDT7012L55L48 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x9 Dual-Port SRAM |
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