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參數(shù)資料
| 型號： | IDT70101S35L52 |
| 英文描述： | x9 Dual-Port SRAM |
| 中文描述： | X9熱賣雙端口SRAM |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 190K |
| 代理商： | IDT70101S35L52 |
6.42
IDT70V9379L
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
12
Timing Waveform of Pipelined Read with Address Counter Advance(1)
Timing Waveform of Flow-Through Read with Address Counter Advance(1)
NOTES:
1.
CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via
ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data
output remains constant for subsequent clocks.
ADDRESS
An
CLK
DATAOUT
Qx - 1
(2)
Qx
Qn
Qn + 2
(2)
Qn + 3
ADS
CNTEN
tCYC2
tCH2
tCL2
4857 drw 14
tSA
tHA
tSAD tHAD
tCD2
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
tSAD tHAD
tSCN tHCN
READ
WITH
COUNTER
Qn + 1
ADDRESS
An
CLK
DATAOUT
Qx
(2)
Qn
Qn + 1
Qn + 2
Qn + 3
(2)
Qn + 4
ADS
CNTEN
tCYC1
tCH1
tCL1
4857 drw 15
tSA
tHA
tSAD tHAD
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
tCD1
tDC
tSAD tHAD
tSCN tHCN
READ
WITH
COUNTER
相關PDF資料 |
PDF描述 |
|---|---|
| IDT70101S35L52B | x9 Dual-Port SRAM |
| IDT70101S45J | x9 Dual-Port SRAM |
| IDT70101S45L52 | x9 Dual-Port SRAM |
| IDT70101S45L52B | x9 Dual-Port SRAM |
| IDT70101S55J | x9 Dual-Port SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT70101S35L52B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70101S45J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70101S45L52 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70101S45L52B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70101S55J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
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