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參數(shù)資料
| 型號(hào)： | IDT70101L55L52B |
| 英文描述： | x9 Dual-Port SRAM |
| 中文描述： | X9熱賣雙端口SRAM |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 190K |
| 代理商： | IDT70101L55L52B |
6.42
IDT70V9379L
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
10
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3.
CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
R/W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
DATAIN
Dn + 2
CE0
CLK
4857 drw 10
Qn
Qn + 3
DATAOUT
CE1
UB, LB
tCD2
tCKHZ
tCKLZ
tCD2
tSC
tHC
tSB
tHB
tSW tHW
tSA
tHA
tCH2
tCL2
tCYC2
READ
NOP
READ
tSD tHD
(4)
(2)
(1)
tSW tHW
WRITE
(5)
R/W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
An + 5
DATAIN
Dn + 3
Dn + 2
CE0
CLK
4857 drw 11
DATAOUT
Qn
Qn + 4
CE1
UB, LB
OE
tCH2
tCL2
tCYC2
tCKLZ(1)
tCD2
tOHZ(1)
tCD2
tSD tHD
READ
WRITE
READ
tSC
tHC
tSB
tHB
tSW tHW
tSA
tHA
(4)
(2)
tSW tHW
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| IDT70101S35J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70101S35L52 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
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