參數(shù)資料
型號(hào): IDT7009L20PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: Sealed Serial Bus Connector; Connector Shell Back Termination:USB-A Receptacle; Connector Shell Finish:Black Coating; Data Rate:1024Mbps; Features:Protective Cap; Series:USBFTV; USB Connector Shell Style:Square Flange Receptacle RoHS Compliant: Yes
中文描述: 128K X 8 DUAL-PORT SRAM, 20 ns, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
文件頁(yè)數(shù): 6/17頁(yè)
文件大?。?/td> 143K
代理商: IDT7009L20PF
6
IDT7009L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
$A9A9A
;<2/
'#
NOTES:
1. Timng depends on which signal is asserted last,
OE
or
CE
.
2. Timng depends on which signal is de-asserted first
CE
or
OE
.
3. t
BDD
delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY
has no relation to valid output data.
4. Start of valid data depends on which timng becomes effective last t
AOE
, t
ACE
, t
AA
or t
BDD
.
5.
SEM
= V
IH
.
6. Refer to Chip Enable Truth Table.
$2
Figure 2. Output Test Load
(for t
LZ
, t
HZ
, t
WZ
, t
OW
)
*Including scope and jig.
Figure 1. AC Output Test Load
4839 drw 04
893
30pF
347
5V
DATA
OUT
BUSY
INT
893
5pF*
347
5V
DATA
OUT
4839 drw 03
t
RC
R/
W
CE
(6)
ADDR
t
AA
t
ACE
OE
4839 drw 05
(4)
(4)
t
AOE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
CE
4839 drw 06
t
PU
I
CC
I
SB
t
PD
(6)
50%
50%
.
Input Pulse Levels
Input Rise/Fall Times
Input Timng Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1 and 2
4839 tbl 11
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