參數(shù)資料
型號(hào): IDT7008L55G
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): DRAM
英文描述: HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM
中文描述: 64K X 8 DUAL-PORT SRAM, 55 ns, CPGA84
封裝: 1.12 X 1.12 INCH, 0.16 INCH HEIGHT, PGA-84
文件頁(yè)數(shù): 13/19頁(yè)
文件大小: 167K
代理商: IDT7008L55G
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
3198 drw 13
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/
W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
$.8.%**+,,
BUSY
2
-
S
09
'C
B
$.8.%
BUSY
-
S
09
'D
NOTES:
1. To ensure that the earlier of the two ports wins. t
APS
is ignored for M/
S
= V
IL
(SLAVE).
2.
CE
L
=
CE
R
= V
IL,
refer to Chip Enable Truth Table.
3.
OE
= V
IL
for the reading port.
4. If M/
S
= V
IL
(SLAVE), then
BUSY
is an input (
BUSY
"A"
= V
IH
and
BUSY
"B"
= "don't care", for this example).
5. All timng is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite fromport "A".
NOTES:
1. t
WH
must be met for both
BUSY
input (SLAVE) and output (MASTER).
2.
BUSY
is asserted on port "B" blocking R/W
"B"
, until
BUSY
"B"
goes HIGH.
3. t
WB
is only for the 'Slave' version.
3198 drw 14
R/
W
"A"
BUSY
"B"
t
WP
t
WB
(3)
R/
W
"B"
t
WH
(1)
(2)
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