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參數(shù)資料
| 型號(hào)： | IDT7008L35G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 64K X 8 DUAL-PORT SRAM, 35 ns, CPGA84 |
| 封裝： | 1.12 X 1.12 INCH, 0.16 INCH HEIGHT, PGA-84 |
| 文件頁(yè)數(shù)： | 10/19頁(yè) |
| 文件大?。?/td> | 167K |
| 代理商： | IDT7008L35G |
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10
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
$.8.7#"+-
W
,$
2A
$.8.7#"
CE
,$
2
NOTES:
1. R/
W
or
CE
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of a LOW
CE
and a LOW R/
W
for memory array writing cycle.
3. t
WR
is measured fromthe earlier of
CE
or R/
W
(or
SEM
or R/
W
) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE
or
SEM
LOW transition occurs simultaneously with or after the R/
W
LOW transition, the outputs remain in the High-impedance state.
6. Timng depends on which enable signal is asserted last,
CE
or R/
W
.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV fromsteady state with the Output Test Load (Figure
2).
8. If
OE
is LOW during R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t
DW
. If
OE
is HIGH during an R/
W
controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified t
WP
.
9. To access RAM
CE
= V
IL
and
SEM
= V
IH
. To access semaphore,
CE
= V
IH
and
SEM
= V
IL
. t
EW
must be met for either condition.
10. Refer to Chip Enable Truth Table.
R/
W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
CE
or
SEM
(6)
(4)
(4)
(3)
3198 drw 09
(7)
(7)
(9,10)
3198 drw 10
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/
W
t
AW
t
EW
(3)
(2)
(6)
CE
or
SEM
(9,10)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7008L35GB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM |
| IDT7008L35GI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM |
| IDT7008L35J | 功能描述:IC SRAM 512KBIT 35NS 84PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT7008L35J8 | 功能描述:IC SRAM 512KBIT 35NS 84PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT7008L35JB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM |
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