參數(shù)資料
型號: IDT7008L25GB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM
中文描述: 64K X 8 DUAL-PORT SRAM, 25 ns, CPGA84
封裝: 1.12 X 1.12 INCH, 0.16 INCH HEIGHT, PGA-84
文件頁數(shù): 8/19頁
文件大小: 167K
代理商: IDT7008L25GB
8
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
$*@*
.8+,7
2
NOTES:
1. Timng depends on which signal is asserted last,
OE
or
CE
.
2. Timng depends on which signal is de-asserted first
CE
or
OE
.
3. t
BDD
delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY
has no relation to valid output data.
4. Start of valid data depends on which timng becomes effective last t
AOE
, t
ACE
, t
AA
or t
BDD
.
5.
SEM
= V
IH
.
6. Refer to Chip Enable Truth Table.
$,
Figure 2. Output Test Load
(for t
LZ
, t
HZ
, t
WZ
, t
OW
)
*Including scope and jig.
Figure 1. AC Output Test Load
3198 drw 06
893
30pF
347
5V
DATA
OUT
BUSY
INT
893
5pF*
347
5V
DATA
OUT
3198 drw 05
t
RC
R/
W
CE
(6)
ADDR
t
AA
t
ACE
OE
3198 drw 07
(4)
(4)
t
AOE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
CE
3198 drw 08
t
PU
I
CC
I
SB
t
PD
(6)
,
Input Pulse Levels
Input Rise/Fall Times
Input Timng Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns Max.
1.5V
1.5V
Figures 1 and 2
3198 tbl 11
相關PDF資料
PDF描述
IDT7008L25GI HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM
IDT7008L25J HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM
IDT7008L25JB HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM
IDT7008L25JI HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM
IDT7008L25PF HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM
相關代理商/技術參數(shù)
參數(shù)描述
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