參數(shù)資料
型號: IDT7006S55J
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: Single Synchronous Buck PWM Controller
中文描述: 16K X 8 DUAL-PORT SRAM, 55 ns, PQCC68
封裝: 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68
文件頁數(shù): 11/20頁
文件大?。?/td> 263K
代理商: IDT7006S55J
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.07
11
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE
(1)
NOTES:
1.
CE
= V
IH
for the duration of the above timing (both write and read cycle).
2. "DATA
OUT
VALID" represents all I/O's (I/O
0
-I/O
7
) equal to the semaphore value.
NOTES:
1. D
OR
= D
OL
= V
IL
,
CE
R
=
CE
L
= V
IH
, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/
W
"A"
or
SEM
"A"
going High to R/
W
"B"
or
SEM
"B"
going High.
4. If t
SPS
is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION
(1,3,4)
SEM
"A"
2739 drw 12
t
SPS
MATCH
R/
W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE
“A”
(2)
SEM
"B"
R/
W
"B"
A
0"B"
-A
2"B"
SIDE
“B”
(2)
SEM
2739 drw 11
t
AW
t
EW
t
SOP
I/O
VALID ADDRESS
t
SAA
R/
W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA
IN
VALID
DATA
OUT
VALID
(2)
t
DW
t
WP
t
DH
t
AS
t
SWRD
t
AOE
Read Cycle
Write Cycle
A
0
-A
2
OE
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IDT7006S55L68 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM