參數(shù)資料
型號: IDT7006S15F
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: 800mA 3MHz Digitally Programmable DC/DC converter; Package: WL-CSP; No of Pins: 12; Container: Tape & Reel
中文描述: 16K X 8 DUAL-PORT SRAM, 15 ns, PQFP68
封裝: 0.970 X 0.970 INCH, 0.080 INCH HEIGHT, QFP-68
文件頁數(shù): 12/20頁
文件大?。?/td> 263K
代理商: IDT7006S15F
6.07
12
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and
BUSY
".
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
– t
WP
(actual), or t
DDD
– t
DW
(actual).
4. To ensure that the write cycle is inhibited with port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention with port "A".
6. "X" is part numbers indicates power rating (S or L).
2739 tbl 15
BUSY TIMING (M/
S
= V
IL
)
BUSY
Input to Write
(4)
Write Hold After
BUSY
(5)
t
WB
0
0
0
ns
t
WH
25
25
25
ns
PORT-TO-PORT DELAY TIMING
Write Pulse to Data Delay
(1)
Write Data Valid to Read Data Delay
(1)
t
WDD
60
80
95
ns
t
DDD
45
65
80
ns
IDT7006X35
IDT7006X55
IDT7006X70
Mil. Only
Min.
Symbol
BUSY TIMING (M/
S
= V
IH
)
t
BAA
BUSY
Access Time from Address Match
t
BDA
BUSY
Disable Time from Address Not Matched
t
BAC
BUSY
Access Time from Chip Enable Low
t
BDC
BUSY
Disable Time from Chip Enable High
t
APS
Arbitration Priority Set-up Time
(2)
BUSY
Disable to Valid Data
(3)
Write Hold After
BUSY
(5)
Parameter
Min.
Max.
Min.
Max.
Max.
Unit
5
20
20
20
20
5
45
40
40
35
5
45
40
40
35
ns
ns
ns
ns
ns
t
BDD
35
40
45
ns
t
WH
25
25
25
ns
BUSY TIMING (M/
S
= V
IL
)
t
WB
BUSY
Input to Write
(4)
Write Hold After
BUSY
(5)
PORT-TO-PORT DELAY TIMING
Write Pulse to Data Delay
(1)
Write Data Valid to Read Data Delay
(1)
0
0
0
0
ns
t
WH
12
13
15
17
ns
t
WDD
30
30
45
50
ns
t
DDD
25
25
35
35
ns
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(6)
IDT7006X15 IDT7006X17
Com'l. Only Com'l. Only
Parameter Min. Max. Min.
IDT7006X20
IDT7006X25
Symbol
BUSY TIMING (M/
S
= V
IH
)
t
BAA
BUSY
Access Time from Address Match
t
BDA
BUSY
Disable Time from Address Not Matched
t
BAC
BUSY
Access Time from Chip Enable Low
t
BDC
BUSY
Disable Time from Chip Enable High
t
APS
Arbitration Priority Set-up Time
(2)
t
BDD
BUSY
Disable to Valid Data
(3
t
WH
Write Hold After
BUSY
(5)
Max.
Min.
Max.
Min.
Max.
Unit
5
12
15
15
15
15
18
5
13
17
17
17
17
18
5
15
20
20
20
17
30
5
17
20
20
20
17
35
ns
ns
ns
ns
ns
ns
ns
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