參數(shù)資料
型號(hào)： IDT7005S55FB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： PWM and ULDO Controller Combo; Package: SOIC; No of Pins: 16; Container: Tape & Reel
中文描述： 8K X 8 DUAL-PORT SRAM, 55 ns, QFP68
封裝： 0.970 X 0.970 INCH, 0.080 INCH HEIGHT, QFP-68
文件頁(yè)數(shù)： 4/20頁(yè)
文件大?。?/td> 265K
代理商： IDT7005S55FB
6.06
12
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tWH
Write Hold After
BUSY(5)
25
—
25
—
25
—
ns
BUSY TIMING (M/
SSSSS = VIL)
tWB
BUSY Input to Write(4)
0—
ns
tWH
Write Hold After
BUSY
(5)
25
—
25
—
25
—
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay
(1)
—60—80
—95
ns
tDDD
Write Data Valid to Read Data Delay
(1)
—45—65
—80
ns
BUSY TIMING (M/
SSSSS = VIL)
tWB
BUSY Input to Write(4)
0
—
0
—
0
—
0
—
ns
tWH
Write Hold After
BUSY
(5)
12
—
13
—
15
—
17
—
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay
(1)
—
30
—
30
—
45
—
50
ns
tDDD
Write Data Valid to Read Data Delay
(1)
—
25
—25—35
—35
ns
IDT7005X15 IDT7005X17
IDT7005X20
IDT7005X25
Com'l. Only
Symbol
Parameter
Min. Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/
SSSSS = VIH)
tBAA
BUSY Access Time from Address Match
—
15
—
17
—
20
—
20
ns
tBDA
BUSY Disable Time from Address Not Matched —
15
—
17
—
20
—
20
ns
tBAC
BUSY Access Time from Chip Enable Low
—
15
—
17
—
20
—
20
ns
tBDC
BUSY Disable Time from Chip Enable High
—
15
—
17
—
17
—
17
ns
tAPS
Arbitration Priority Set-up Time
(2)
5
—
5
—
5
—
5
—
ns
tBDD
BUSY Disable to Valid Data
(3)
—
18
—
18
—
30
—
30
ns
tWH
Write Hold After
BUSY(5)
12
—
13
—
15
—
17
—
ns
IDT7005X35
IDT7005X55
IDT7005X70
Mil. Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/
SSSSS = VIH)
tBAA
BUSY Access Time from Address Match
—
20
—
45
—
45
ns
tBDA
BUSY Disable Time from Address Not Matched
—
20
—
40
—
40
ns
tBAC
BUSY Access Time from Chip Enable Low
—
20
—
40
—
40
ns
tBDC
BUSY Disable Time from Chip Enable High
—
20
—
35
—
35
ns
tAPS
Arbitration Priority Set-up Time
(2)
5—
ns
tBDD
BUSY Disable to Valid Data(3)
—35—40
—45
ns
NOTES:
2738 tbl 15
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and
BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention with port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. "X" in part numbers indicates power rating (S or L).
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT7005S55G 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
IDT7005S55GB 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 64KBIT 55NS 68PGA
IDT7005S55J 功能描述:IC SRAM 64KBIT 55NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤(pán) 其它名稱:71V67703S75PFGI
IDT7005S55J8 功能描述:IC SRAM 64KBIT 55NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤(pán) 其它名稱:71V67703S75PFGI
IDT7005S55JB 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
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