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參數(shù)資料
| 型號： | IDT7005L70PF |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 高速8K的× 8雙端口靜態(tài)RAM |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 265K |
| 代理商： | IDT7005L70PF |
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.06
15
WAVEFORM OF INTERRUPT TIMING(1)
TRUTH TABLES
TRUTH TABLE I — INTERRUPT FLAG(1,4)
Left Port
Right Port
R/
W
WL
CE
CEL
OE
OEL A12L-A0L INT
INT
INTL
R/
W
WR
CE
CER
OE
OER A12R-A0R INT
INT
INTR
Function
L
X
1FFF
XXXXX
L
(2)
Set Right
INTR Flag
X
L
1FFF
H
(3)
Reset Right
INTR Flag
XX
X
L
(3)
L
X
1FFE
X
Set Left
INTL Flag
X
L
1FFE
H
(2)
XXXXX
Reset Left
INTL Flag
NOTES:
2738 tbl 17
1. Assumes
BUSYL = BUSYR = VIH.
2. If
BUSYL = VIL, then no change.
3. If
BUSYR = VIL, then no change.
4.
INTR and INTL must be initialized at power-up.
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal (
CE or R/W) asserted last.
4. Timing depends on which enable signal (
CE or R/W) is de-asserted first.
2738 drw 18
ADDR"B"
INTERRUPT CLEAR ADDRESS
CE"B"
OE"B"
tAS
tRC
(3)
tINR(3)
INT"B"
(2)
2738 drw 17
ADDR"A"
INTERRUPT SET ADDRESS
CE"A"
R/
W"A"
tAS
tWC
tWR
(3)
(4)
tINS (3)
INT"B"
(2)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7005L70PFB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
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| IDT7005S | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
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| IDT7005S15FB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
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