參數(shù)資料
型號: IDT7005L55F
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: Single, Ultra Low Cost, RRIO CMOS Amplifier
中文描述: 8K X 8 DUAL-PORT SRAM, 55 ns, QFP68
封裝: 0.970 X 0.970 INCH, 0.080 INCH HEIGHT, QFP-68
文件頁數(shù): 5/20頁
文件大?。?/td> 265K
代理商: IDT7005L55F
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.06
13
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ WITH
BUSY
BUSY (M/S = VIH)(2,4,5)
NOTES:
1. tWH must be met for both
BUSY input (slave) and output (master).
2.
BUSY is asserted on Port "B" Blocking R/W"B", until BUSY"B" goes High.
3. tWB is only for the 'Slave' Version.
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for for M/
S = VIL (slave).
2.
CEL = CER = VIL.
3.
OE = VIL for the reading port.
4. If M/
S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite port "A".
2738 drw 13
tDW
tAPS
ADDR"A"
tWC
DATAOUT "B"
MATCH
tWP
R/
W"A"
DATAIN "A"
ADDR"B"
tDH
VALID
(1)
MATCH
BUSY"B"
tBDA
VALID
tBDD
tDDD
(3)
tWDD
2738 drw 14
R/
W"A"
BUSY"B"
tWP
tWB
R/
W"B"
tWH
(2)
(3)
(1)
TIMING WAVEFORM OF WITH WRITE
BUSY
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相關代理商/技術參數(shù)
參數(shù)描述
IDT7005L55FB 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
IDT7005L55G 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
IDT7005L55GB 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 64KBIT 55NS 68PGA
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IDT7005L55J8 功能描述:IC SRAM 64KBIT 55NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M(256K x 36) 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應商設備封裝:100-TQFP(14x14) 包裝:托盤 其它名稱:71V67703S75PFGI