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參數(shù)資料
| 型號(hào)： | IDT7005L45GB |
| 英文描述： | x8 Dual-Port SRAM |
| 中文描述： | x8雙端口SRAM |
| 文件頁(yè)數(shù)： | 5/15頁(yè) |
| 文件大?。?/td> | 190K |
| 代理商： | IDT7005L45GB |
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6.42
IDT70V9379L
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
13
ADDRESS
(4)
An
D0
tCH2
tCL2
tCYC2
Q0
Q1
0
CLK
DATAIN
R/W
CNTRST
4857 drw 17
INTERNAL
(3)
ADDRESS
ADS
CNTEN
tSRST tHRST
tSD
tHD
tSW tHW
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
Qn
An + 1
An + 2
READ
ADDRESS n+1
DATAOUT
(5)
tSA tHA
1
An
An + 1
(6)
Ax
tSAD tHAD
tSCN tHCN
(6)
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
ADDRESS
An
CLK
DATAIN
Dn
Dn + 1
Dn + 2
ADS
CNTEN
(7)
tCH2
tCL2
tCYC2
4857 drw 16
INTERNAL
(3)
ADDRESS
An
(7)
An + 1
An + 2
An + 3
An + 4
Dn + 3
Dn + 4
tSA
tHA
tSAD tHAD
WRITE
COUNTER HOLD
WRITE WITH COUNTER
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
tSD tHD
NOTES:
1.
CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
2. CE0, UB, LB = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when
ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since
ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles
are shown here simply for clarification.
7.
CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance.
The ‘An +1’ Address is written to during this cycle.
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| IDT7005L45J | 功能描述:IC SRAM 64KBIT 45NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT7005L45J8 | 功能描述:IC SRAM 64KBIT 45NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT7005L45L68 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| IDT7005L45L68B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| IDT7005L45PF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
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