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參數(shù)資料
| 型號(hào)： | IDT7005L35PFB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Single, Ultra Low Cost, RRIO CMOS Amplifier; Package: SC70; No of Pins: 5; Container: Tape & Reel |
| 中文描述： | 8K X 8 DUAL-PORT SRAM, 35 ns, PQFP64 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-64 |
| 文件頁(yè)數(shù)： | 3/20頁(yè) |
| 文件大?。?/td> | 265K |
| 代理商： | IDT7005L35PFB |
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IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.06
11
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
NOTES:
1.
CE = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O7) equal to the semaphore value.
SEM"A"
2738 drw 12
tSPS
MATCH
R/
W"A"
MATCH
A0"A"-A2"A"
SIDE
“A”
(2)
SEM"B"
R/
W"B"
A0"B"-A2"B"
SIDE
“B”
(2)
NOTES:
1. DOR = DOL = VIL,
CER = CEL = VIH. Semaphore flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. “B” is the opposite from port “A”.
3. This parameter is measured from R/
W"A" or SEM"A" going High to R/W"B" or SEM"B" going High.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
SEM
2738 drw 11
tAW
tEW
tSOP
I/O
VALID ADDRESS
tSAA
R/
W
tWR
tOH
tACE
VALID ADDRESS
DATAIN
VALID
DATAOUT
tDW
tWP
tDH
tAS
tSWRD
tAOE
Read Cycle
Write Cycle
A0-A2
OE
VALID(2)
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相關(guān)代理商/技術(shù)參數(shù) |
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| IDT7005L35XL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| IDT7005L35XLB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| IDT7005L45F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| IDT7005L45FB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| IDT7005L45G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
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