參數(shù)資料
型號(hào): IDT7005L25PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: Dual 2A High-Speed, Low-Side Gate Driver; Package: SOIC; No of Pins: 8; Container: Tape & Reel
中文描述: 8K X 8 DUAL-PORT SRAM, 25 ns, PQFP64
封裝: 14 X 14 MM, 1.40 MM HEIGHT, TQFP-64
文件頁數(shù): 19/20頁
文件大?。?/td> 265K
代理商: IDT7005L25PF
6.06
8
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
NOTES:
1. Timing depends on which signal is asserted last,
OE or CE.
2. Timing depends on which signal is de-asserted first,
CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5.
SEM = VIH.
CE
2738 drw 08
tPU
ICC
ISB
tPD
50%
tRC
R/
W
CE
ADDR
tAA
OE
2738 drw 07
(4)
tACE
(4)
tAOE
(4)
(1)
tLZ
tOH
(2)
tHZ
(3, 4)
tBDD
DATAOUT
BUSYOUT
VALID DATA
(4)
TIMING OF POWER-UP POWER-DOWN
相關(guān)PDF資料
PDF描述
IDT7005L25PFB Dual 2A High-Speed, Low-Side Gate Driver; Package: MLP; No of Pins: 8; Container: Tape & Reel
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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