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參數(shù)資料
| 型號(hào)： | IDT6178S25DB |
| 廠(chǎng)商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM |
| 中文描述： | 4K X 4 CACHE TAG SRAM, 25 ns, CDIP22 |
| 封裝： | 0.300 INCH, CERAMIC, DIP-22 |
| 文件頁(yè)數(shù)： | 6/7頁(yè) |
| 文件大小： | 72K |
| 代理商： | IDT6178S25DB |
11.1
6
IDT6178S
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, All Temperature Ranges)
6178S10
(1)
6178S12
6178S15
6178S20/25
Symbol
Write Cycle
t
WC
t
AW
t
AS
t
WP
t
WR
t
DW
t
DH
t
WHZ
(2)
t
OW
(2)
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Write Cycle Time
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Data Hold from Write Time
Write Enable to Output in High-Z
Output Active from End-of-Write
10
8
0
8
0
6
0
—
0
—
—
—
—
—
—
—
5
—
12
10
0
10
0
8
0
—
0
—
—
—
—
—
—
—
6
—
15
12
0
12
0
10
0
—
0
—
—
—
—
—
—
—
7
—
20
14
0
14
0
12
0
—
0
—
—
—
—
—
—
—
9
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. 0
°
C to +70
°
C temperature range only.
2. This parameter guaranteed with AC load (Figure 3) by device characterization, but is not production tested.
2953 tbl 12
TIMING WAVEFORM OF WRITE CYCLE
(1,3)
NOTES:
1.
WE
must be HIGH during all address transitions.
2. During this period, I/O pins are in the output state and the input signals must not be applied.
3.
OE
is HIGH. If
OE
is LOW during a
WE
controlled write cycle, the write pulse width must be the greater of t
WP
or (
t
WHZ
+ t
DW
)
to allow the I/O drivers to
turn off and data to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the
write pulse is the specified t
WP
.
4. Transition is measured
±
200mV from steady state.
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, All Temperature Ranges)
6178S10
(1)
6178S12
6178S15
6178S20/25
Symbol
Clear Cycle
t
CLPW
(2)
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
CLR
Pulse Width
12
—
15
—
20
—
25
—
ns
t
CLRC
t
POCL
(3)
t
WECL
CLR
HIGH to
WE
LOW
Power on Reset
WE
HIGH to Clear HIGH
5
—
—
—
5
60
5
—
—
—
5
80
5
—
—
—
5
—
—
—
ns
ns
ns
50
5
100
5
NOTES:
1. 0
°
C to +70
°
C temperature range only.
2. Recommended duty cycle of 10% maximum.
3. This parameter guaranteed with AC load (Figure 3) by device characterization, but is not production tested.
2953 tbl 13
ADDRESS
t
WC
t
AW
DATA
OUT
DATA
IN
WE
t
AS
t
WP
t
WR
t
WHZ
t
OW
(4)
t
DH
DATA
IN
VALID
t
DW
(4)
(4)
(4)
2953 drw 10
(2)
(2)
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IDT6178S25P | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM |
| IDT6178S25PB | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM |
| IDT6178S25Y | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM |
| IDT6178S25YB | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM |
| IDT61970L20D | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x4 SRAM |
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