參數(shù)資料
型號(hào): IDT5V9910A-2SOC
英文描述: EIGHT DISTRIBUTED-OUTPUT CLOCK DRIVER|SOP|24PIN|PLASTIC
中文描述: 八分布式輸出時(shí)鐘驅(qū)動(dòng)器|??苵 24針|塑料
文件頁數(shù): 4/6頁
文件大?。?/td> 95K
代理商: IDT5V9910A-2SOC
4
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT5V9910A
3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
NOTES:
1. All timing and jitter tolerances apply for F
NOM
25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load.
3. t
SKEW
is the skew between all outputs. See AC test loads.
4. For IDT5V9910A-2, t
SKEW0
is measured with C
L
= 0pF; for C
L
= 20pF, t
SKEW0
= 0.35ns max.
5. t
DEV
is the output-to-output skew between any two devices operating under the same conditions (V
CC
, ambient temperature, air flow, etc.)
6. t
LOCK
is the time that is required before synchronization is achieved. This specification is valid only after V
CC
is stable and within normal operating
limits. This parameter is measured from the application of a new signal or frequency at REF or FB until t
PD
is within specified limits.
7. t
PD
is measured with REF input rise and fall times (from 0.8V to 2V) of 1ns.
8. Refer to Input Timing Requirements for more detail.
INPUT TIMING REQUIREMENTS
Symbol
t
R
, t
F
t
PWC
D
H
R
EF
Description
(1)
Mn.
3
10
15
Max.
10
90
85
Unit
ns/V
ns
%
MHz
Maximuminput rise and fall times, 0.8V to 2V
Input clock pulse, HIGH or LOW
Input duty cycle
Reference Clock Input
NOTE:
1. Where pulse width implied by D
H
is less than t
PWC
limit, t
PWC
limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT5V9910A-2
Mn.
Typ.
15
25
40
3
3
0.25
1.2
0.15
0.15
IDT5V9910A-5
Mn.
Typ.
15
25
40
0.25
0.5
1.2
0.15
0.15
IDT5V9910A-7
Mn.
Typ.
15
25
40
3
3
0.7
1.2
0.15
0.15
Symbol
F
REF
Parameter
Max.
35
60
85
0.25
0.75
0.25
1.2
1.8
1.8
0.5
25
200
Max.
35
60
85
0.5
1.25
0.5
1.2
1.8
1.8
0.5
40
200
Max.
35
60
85
0.75
1.65
0.7
1.2
2.5
2.5
0.5
40
200
Unit
MHz
REF Frequency Range
FS = LOW
FS = MID
FS = HIGH
0.1
0
0
1
1
0.3
0
0
1.5
1.5
t
RPWH
t
RPWL
t
SKEW0
t
DEV
t
PD
t
ODCV
t
ORISE
t
OFALL
t
LOCK
t
JR
REF Pulse Width HIGH
(8)
REF Pulse Width LOW
(8)
Zero Output Skew (All Outputs)
(1,3,4)
Device-to-Device Skew
(1,2,5)
REF Input to FB Propagation Delay
(1,7)
Output Duty Cycle Variation from50%
(1)
Output Rise Time
(1)
Output Fall Time
(1)
PLL Lock Time
(1,6)
Cycle-to-Cycle Output Jitter
(1)
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
0
0
1
1
RMS
Peak-to-Peak
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