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參數(shù)資料
| 型號： | IDT5V2528PGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 5V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | TSSOP-28 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 72K |
| 代理商： | IDT5V2528PGI8 |
1
INDUSTRIALTEMPERATURERANGE
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
JUNE 2003
2002
Integrated Device Technology, Inc.
DSC 5971/12
c
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Operates at 3.3V VDD/AVDD and 2.5V/3.3V VDDQ
1:10 fanout
3-level inputs for output control
External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
No external RC network required for PLL loop stability
Configurable 2.5V or 3.3V LVTTL outputs
tPD Phase Error at 100MHz to 166MHz: ±150ps
Jitter (peak-to-peak) at 133MHz and 166MHz: ±75ps
Spread spectrum compatible
Operating Frequency:
Std: 25MHz to 140MHz
A: 25MHz to 167MHz
Available in TSSOP package
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT5V2528 is a high performance, low-skew, low-jitter, phase-lock
loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency
and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
IDT5V2528/A
2.5V / 3.3V PHASE-LOCK
LOOP CLOCK DRIVER
ZERO DELAY BUFFER
19
Y1, VDD pin 21
PLL
3
24
17
16
26
TY0, VDDQ pin 4
13
10
20
12
Y0, VDD pin 21
6
7
5
AVDD
FBIN
CLK
G_Ctrl
28
22
FBOUT, VDD pin 21
T_Ctrl
1
MODE
SELECT
TY1, VDDQ pin 25
TY2, VDDQ pin 25
TY3, VDDQ pin 15
TY4, VDDQ pin 15
TY5, VDDQ pin 11
TY6, VDDQ pin 11
TY7, VDDQ pin 11
The IDT5V2528 inputs, PLL core, Y0, Y1, and FBOUT buffers operate from
the 3.3V VDD and AVDD power supply pins.
One bank of ten outputs provide low-skew, low-jitter copies of CLK. Of
the ten outputs, up to seven may be configured for 2.5V or 3.3V LVTTL
outputs. The number of 2.5V outputs is controlled by 3-level input signals
G_Ctrl and T_Ctrl, and by connecting the appropriate VDDQ pins to 2.5V or
3.3V. The 3-level input signals may be hard-wired to high-mid-low levels.
Output signal duty cycles are adjusted to 50 percent, independent of the duty
cycle at CLK. The outputs can be enabled or disabled via the G_Ctrl input.
When the G_Ctrl input is mid or high, the outputs switch in phase and
frequency with CLK; when the G_Ctrl is low, all outputs (except FBOUT) are
disabled to the logic-low state.
Unlike many products containing PLLs, the IDT5V2528 does not require
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the IDT5V2528 requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power up and
application of a fixed-frequency, fixed-phase signal at CLK, as well as
following any changes to the PLL reference or feedback signals. The PLL
can be bypassed for test purposes by strapping AVDD to ground.
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