參數(shù)資料
型號(hào): IDT5T9821NLGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 5T SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC68
封裝: GREEN, PLASTIC, VFQFPN-68
文件頁(yè)數(shù): 1/36頁(yè)
文件大小: 277K
代理商: IDT5T9821NLGI
1
INDUSTRIALTEMPERATURERANGE
IDT5T9821
EEPROMPROGRAMMABLE2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER
NOVEMBER 2004
2004
Integrated Device Technology, Inc.
DSC - 6502/20
c
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
2.5 VDD
6 pairs of outputs
Low skew: 100ps all outputs at same interface level, 250ps all
outputs at different interface levels
Selectable positive or negative edge synchronization
Tolerant of spread spectrum input clock
Synchronous output enable
Selectable inputs
Input frequency: 4.17MHz to 250MHz
Output frequency: 12.5MHz to 250MHz
Internal non-volatile EEPROM
JTAG or I2C bus serial interface for programming
Hot insertable and over-voltage tolerant inputs
Feedback divide selection with multiply ratios of (1-6, 8, 10, 12)
Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input
interface
Selectable HSTL, eHSTL, or 1.8V/2.5V LVTTL output interface for
each output bank
Selectable differential or single-ended inputs and six differen-
tial outputs
PLL bypass for DC testing
External differential feedback, internal loop filter
Low Jitter: <75ps cycle-to-cycle, all outputs at same interface
level: <100ps cycle-to-cycle all outputs at different interface
levels
Power-down mode
Lock indicator
Available in VFQFPN package
IDT5T9821
EEPROM PROGRAMMABLE 2.5V
ZERO DELAY PLL DIFFERENTIAL
CLOCK DRIVER
DESCRIPTION:
The IDT5T9821 is a 2.5V PLL differential clock driver intended for high
performance computing and data-communications applications. The
IDT5T9821 has six differential outputs in six banks, including a dedicated
differential feedback. The redundant input capability allows for a smooth
change over to a secondary clock source when the primary clock source
is absent.
The clock driver can be configured through the use of JTAG/I2C program-
ming. An internal EEPROM will allow the user to save and restore the
configuration of the device.
The feedback bank allows divide-by-functionality from 1 to 12 through
the use of JTAG or I2C programming. This provides the user with frequency
multiplication 1 to 12 without using divided outputs for feedback. Each output
bank also allows for a divide-by functionality of 2 or 4.
The IDT5T9821 features a user-selectable, single-ended or differential
input to six differential outputs. The differential clock driver also acts as a
translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or
single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL
outputs. Each output bank can be individually configured to be either HSTL,
eHSTL,2.5VLVTTL,or1.8VLVTTL,includingthefeedbackbank. Also,each
clock input can be individually configured to accept 2.5V LVTTL, 1.8V LVTTL,
or differential signals. The outputs can be synchronously enabled/disabled.
The differential outputs can be synchronously enabled/disabled.
Furthermore, all the outputs can be synchronized with the positive edge
of the REF clock input. or the negative edge of REF.
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